Patents by Inventor Joseph K. So

Joseph K. So has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6530824
    Abstract: A polishing composition for polishing a semiconductor wafer includes a source of chloride ions in solution, which reduces surface roughness of copper interconnects that are recessed in the wafer. High points on the copper interconnects are polished during a polishing operation, while the chloride ions migrate to electric fields concentrated at the high points. The chloride ions at the high points deter replating of copper ions from solution onto the high points. Instead the copper ions replate elsewhere on the interconnects, which reduces the surface roughness of the interconnects.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: March 11, 2003
    Assignee: Rodel Holdings, Inc.
    Inventors: Terence M. Thomas, Qianqiu Christine Ye, Joseph K. So, Wendy B. Goldberg, Wade Godfrey
  • Patent number: 6475069
    Abstract: A method for CMP polishing with a first step slurry composition selective to a metal in a metal layer to remove the metal at a high removal rate during polishing, and a second step slurry composition selective to a barrier film and least selective to either of an underlying dielectric layer or a metal interconnection structure in the dielectric layer, to remove the barrier film at a high removal rate during polishing, and level a surface of the dielectric layer to the surface of the interconnection structure.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: November 5, 2002
    Assignee: Rodel Holdings, Inc.
    Inventors: Terence M. Thomas, Qianqiu (Christine) Ye, Joseph K. So, Peter A. Burke
  • Publication number: 20020146965
    Abstract: A polishing composition for polishing a semiconductor wafer includes a source of chloride ions in solution, which reduces surface roughness of copper interconnects that are recessed in the wafer. High points on the copper interconnects are polished during a polishing operation, while the chloride ions migrate to electric fields concentrated at the high points. The chloride ions at the high points deter replating of copper ions from solution onto the high points. Instead the copper ions replate elsewhere on the interconnects, which reduces the surface roughness of the interconnects.
    Type: Application
    Filed: March 9, 2001
    Publication date: October 10, 2002
    Inventors: Terence M. Thomas, Qianqiu Ye, Joseph K. So, Wendy B. Goldberg, Wade Godfrey
  • Publication number: 20020019202
    Abstract: A two-step method for chemical mechanical polishing of a semiconductor substrate having successive layers, comprised of, a metal layer, an underlying barrier film and an underlying dielectric layer. The first polishing step is performed utilizing a slurry composition selective to the metal in the metal layer, to remove the metal at a high removal rate during polishing, and the second polishing step is performed utilizing a slurry composition selective to the barrier film and least selective to the metal layer and the underlying dielectric layer. In an alternate embodiment, the second polishing step is performed with a slurry equally selective to the barrier layer and the underlying dielectric layer and least selective to the metal of the metal layer, to remove the barrier layer at a high removal rate during polishing, and level a surface of the dielectric layer to the surface of the metal interconnection structure in the underlying dielectric layer.
    Type: Application
    Filed: February 28, 2001
    Publication date: February 14, 2002
    Inventors: Terence M. Thomas, Qianqiu (Christine) Ye, Joseph K. So, Peter A. Burke, Vikas Sachan, Elizabeth A. Langlois, Keith G. Pierce, Craig D. Lack, David Gettman, Hiroyuki Senoo, Kouchi Yoshida, Yoshikazu Nishida, Vilas N. Koinkar, Raymond Lee Lavoie