Patents by Inventor Joseph Martin Patterson

Joseph Martin Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8907691
    Abstract: A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: December 9, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8506355
    Abstract: A system and method are provided for in-situ inspection optical inspection during a parallel polishing process. The method provides a polishing device with a spindle bit for holding a metallurgical sample, and a rotatable wheel having an inner diameter with a top surface for accepting a polishing compound and a transparent outer diameter. An optical system underlies the wheel outer diameter for recording images of the metallurgical sample. The method polishes the metallurgical sample against the wheel inner diameter. Without releasing the metallurgical sample from the spindle bit, the metallurgical sample is moved to a first position overlying the wheel outer diameter, and the metallurgical sample is optically inspected. In one aspect, the polishing device has a cleaning system overlying the wheel outer diameter, and the method sprays the wheel outer diameter with cleaning solution to support an in-situ inspection.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: August 13, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8427580
    Abstract: A system and method are provided for synchronizing data collected from asynchronously clocked circuitry. The method provides an apparatus having inputs to accept a first clock signal and which has a plurality of devices synchronously timed to a third clock, but asynchronous from the first clock signal. Data frames are simultaneously collected for the plurality of devices, at a second clock repetition rate synchronous to the first clock, of device output detection events responsive to the trigger signal. The second clock repetition rate is greater than the first clock repetition rate. High contrast data frames are saved of device output detection events. A determination is made of a first device in the circuit block acting as the third clock trigger. Saved data frames with first device output detection events are recognized as synchronization frames, and the saved data frames are organized around the synchronization frames.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: April 23, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8394244
    Abstract: A method is provided for laser patterning an integrated circuit (IC) etching mask. The method provides an IC packaged die with a first region underlying a backside surface of a bulk silicon (Si) layer. An etch-resistant film is formed overlying the backside surface. Alternately, the entire IC die package is conformally coated. A semi-transparent film is formed overlying the etch-resistant film, semi-transparent to light having a first wavelength. In response to irradiating the semi-transparent film with light having a first power density, an IC die first region is located. In response to irradiating the semi-transparent film with a laser light having a second power density, greater than the first power density, an area of etch-resistant film overlying the first region is decomposed. More explicitly, an area of semi-transparent film overlying the first region is ablated, and the etch-resistant film underlying the ablated semi-transparent film is heated.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: March 12, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8377749
    Abstract: A method is provided for fabricating a transmission line between electrical circuits. The method initially provides a first electrical circuit with a signal interface and a reference voltage interface, and a second electrical circuit with a signal interface and a reference voltage interface. The first circuit signal interface is connected to the second circuit signal interface with a metal wire. An insulator coating (e.g., poly-para-xylylene) is formed, encapsulating the wire. Then, an electrically conductive coating is formed, encapsulating the insulator coating. Typically, the conductive coating is connected to at least one of the first and second circuit reference voltage interfaces. In one aspect, the first circuit signal interface connection to the second circuit signal interface is a transmission line formed from the combination of the wire, insulator coating, and conductive coating.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: February 19, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8268669
    Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 18, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8188760
    Abstract: A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response to a corresponding base step signal. The signals outputs may be provided to a test fixture, for testing a multi-pin integrated circuit (IC).
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: May 29, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8106671
    Abstract: A socketless integrated circuit (IC) contact connector is provided with an electrically conductive support post. An electrically conductive spring has a first end connected to the post, and a second end. An electrically conductive first wire has a first end connected to the spring second end, and a second end. An electrically conductive loop with a loop neck is connected to the first wire second end. Typically, the loop is formed in the first wire second end. The spring and loop work in cooperation to engage an IC contact.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: January 31, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8106665
    Abstract: A reflector tool and a method are provided for three-dimensional integrated circuit (IC) failure analysis. An IC (die) has top and bottom surfaces, a perimeter, and a first side. The IC is electrically connected to a current sensing amplifier. The first side of the IC is scanned in the X plane with an infrared laser beam while changes in IC current flow are sensed. The sensed current changes are cross-referenced to the location of the infrared laser beam in the X plane. In one aspect, a plurality of scans are performed on the first side in the X plane, with at a corresponding plurality of steps in the Y plane, so that current changes can be cross-referenced to locations in the X and Y planes. Using this 2-D analysis through the IC side, a human operator or software program can determine defects in the IC.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: January 31, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 8106653
    Abstract: System and methods are provided for optical-magnetic Kerr effect signal analysis. In one aspect, a test fixture is supplied having parallel conductive lines, with an input of a first line adjacent a resistively loaded output of a second line and a resistively loaded output of the first line adjacent an input of the second line. An optically transparent test region is interposed between the conductive lines, and a metallic reflector underlies the test region. A signal reference is supplied to the input of the first line and a signal under test is supplied to the input of the second line. A light beam having a first angle of polarization is focused through the test region onto the reflector. The intensity of the reflected light is measured and the similarity between the signal under test and the reference signal can be determined in response to the measured light intensity.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: January 31, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Publication number: 20110169478
    Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.
    Type: Application
    Filed: March 17, 2011
    Publication date: July 14, 2011
    Inventor: Joseph Martin Patterson
  • Patent number: 7977967
    Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: July 12, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7931849
    Abstract: A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 26, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7932119
    Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: April 26, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Patent number: 7916397
    Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 29, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Joseph Martin Patterson
  • Publication number: 20110031993
    Abstract: A curve tracer signal conversion device is provided. The signal conversion device has an input connected to the curve tracer base port to accept a repeating sequence of stepped base signals. The conversion device has a signal input connected to either the curve tracer collector or emitter port, typically the collector. The conversion device has a plurality of signal outputs, where each signal output is sequentially connected to the selected (i.e. collector) curve tracer port in response to a corresponding base step signal. The signals outputs may be provided to a test fixture, for testing a multi-pin integrated circuit (IC).
    Type: Application
    Filed: August 31, 2009
    Publication date: February 10, 2011
    Inventor: Joseph Martin Patterson
  • Publication number: 20100327875
    Abstract: A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Inventor: Joseph Martin Patterson
  • Publication number: 20100289488
    Abstract: System and methods are provided for optical-magnetic Kerr effect signal analysis. In one aspect, a test fixture is supplied having parallel conductive lines, with an input of a first line adjacent a resistively loaded output of a second line and a resistively loaded output of the first line adjacent an input of the second line. An optically transparent test region is interposed between the conductive lines, and a metallic reflector underlies the test region. A signal reference is supplied to the input of the first line and a signal under test is supplied to the input of the second line. A light beam having a first angle of polarization is focused through the test region onto the reflector. The intensity of the reflected light is measured and the similarity between the signal under test and the reference signal can be determined in response to the measured light intensity.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 18, 2010
    Inventor: Joseph Martin Patterson
  • Publication number: 20100277221
    Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.
    Type: Application
    Filed: July 2, 2010
    Publication date: November 4, 2010
    Inventor: Joseph Martin Patterson
  • Publication number: 20100259831
    Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.
    Type: Application
    Filed: June 23, 2010
    Publication date: October 14, 2010
    Inventor: Joseph Martin Patterson