Abstract: A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider.

Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.

Abstract: A method is provided for the electronic processing of analog signals in thermaltronic device. The method accepts an analog input signal, e.g., an AC signal, at a thermaltronic device input and generates a thermal electric (TE) temperature having a first transfer function responsive to the input signal. As opposed to having a digital response, the transfer function is either linear or logarithmic. An analog output signal, e.g., an AC signal, is generated having a second transfer function responsive to the TE, which is likewise either linear or logarithmic.

Abstract: A universal socketless integrated circuit (IC) electrical test fixture is provided. The test fixture is made up of a probing platform to accept and heatsink an IC. The IC has electrical contacts formed on a bottom surface in an array of m rows, where each row includes n, or less contacts. A probe arm includes p probe pins, where p is greater than, or equal to n. A clamping mechanism mechanically interfaces the probe arm probe pins to a row of IC contacts under test. An electrical measurement device has a first interface connected to the p probe pins of the probe arm to measure electrical characteristics associated with the IC contacts under test. The probe arm, clamping mechanism, and probe platform work in cooperation to electrically interface any row of the IC contacts with the electrical measurement device.

Abstract: An optical fiber micro array lens is provided along with an associated fabrication method. The micro array lens is fabricated from a mesh of optical fibers. The mesh includes a first plurality of cylindrical optical fibers. Each fiber from the first plurality has a flat bottom surface and a hemicylindrical top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. The mesh also includes a second plurality of cylindrical optical fibers. Each fiber from the second plurality has a hemicylindrical bottom surface overlying and in contact with the top surfaces of the first plurality of optical fibers, and a flat top surface. The top and bottom surfaces are aligned in parallel with a central fiber axis. Each contact of the first and second plurality of optical fibers forms a lens assembly in a micro array of lenses.

Abstract: A thermal electric (TE) binary NOR gate logic circuit is provided with a method for NOR logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NOR logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.

Abstract: A fixture and method are provided for cooling an IC in the performance of focused beam processes. The method provides a holding/cooling fixture with thermal electric (TE) jaws having an IC interface surface and a heatsink interface. An IC die is secured between the IC interface surfaces of the jaws. Electrical energy is supplied to the TE jaws, creating a negative temperature differential between the IC interface and heatsink interfaces. As a result, the IC die is cooled. A focused beam is applied to a local region of the IC die. Some examples of the focused beam include a focused ion beam (FIB), scanning electron microscope (SEM), E-beam, or a laser scanning microscope (LSM). The focused beam heats the local region of the IC, while the bulk of the IC remains cooled. Typically, each TE jaw includes a plurality of TE elements thermally connected in series.

Abstract: A method is provided for laser optically marking integrated circuit (IC) packages in a non-destructive manner. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. An acute angle is defined between a laser optical path and an IC package planar surface. The IC package surface is scanned with a laser, and in response to ablating the IC package surface, a legible mark on the planar surface.

Abstract: A reflector tool and a method are provided for three-dimensional integrated circuit (IC) failure analysis. An IC (die) has top and bottom surfaces, a perimeter, and a first side. The IC is electrically connected to a current sensing amplifier. The first side of the IC is scanned in the X plane with an infrared laser beam while changes in IC current flow are sensed. The sensed current changes are cross-referenced to the location of the infrared laser beam in the X plane. In one aspect, a plurality of scans are performed on the first side in the X plane, with at a corresponding plurality of steps in the Y plane, so that current changes can be cross-referenced to locations in the X and Y planes. Using this 2-D analysis through the IC side, a human operator or software program can determine defects in the IC.

Abstract: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.

Abstract: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage is accepted representing an input binary logic state, and a second TE temperature is generated in response to the second input voltage. In response to the first and second TE temperatures, a NAND logic state output voltage is generated. More explicitly, a first control voltage is generated in response to the first TE temperature, and a second control voltage is generated in response to the second TE temperature. Then, a third TE temperature is generated in response to the first and second control voltages, which in turn generates the output voltage.

Abstract: A method is provided for the electronic processing of analog signals in thermaltronic device. The method accepts an analog input signal, e.g., an AC signal, at a thermaltronic device input and generates a thermal electric (TE) temperature having a first transfer function responsive to the input signal. As opposed to having a digital response, the transfer function is either linear or logarithmic. An analog output signal, e.g., an AC signal, is generated having a second transfer function responsive to the TE, which is likewise either linear or logarithmic.

Abstract: A thermal electric binary logic circuit is provided along with a method for switching a thermal electric binary logic circuit. The method accepts an input voltage representing an input logic state and generates a thermal electric (TE) temperature value in response to the input voltage. Then, in response to the TE temperature value, a TE voltage is generated and supplied as an output voltage representing an output logic state. In one aspect, a first TE element is connected to the input voltage and to a current source/sink having an intermediate voltage. As a result, the first TE element generates a first temperature reference. A second TE thermally is connected to the first TE, electrically connected to a first voltage reference, and electrically connected to an output to supply the output voltage. As a result, a first voltage varies across the second TE in response to the first temperature.