Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

Abstract: Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell. The combination of the first field and the second field is known to saturate a portion, the synthetic antiferromagnet (SAF), of the MRAM cell being written. This can result in not knowing which logic state is ultimately written. This is known to be worsened at higher temperatures. To avoid this deleterious saturation, the magnetic field is reduced during the time when both fields are applied. This is achieved by reducing the current that provides these fields from the current that is applied when only one of the fields is applied.

Abstract: A magnetoresistive random access memory (MRAM) avoids difficulties with write disturb by electrically isolating the portion of the array with data from the portion with reference signals while providing fast read speeds by simultaneously enabling the word line having the reference cells and the selected word line. For high speed accessing it is difficult to completely stabilize a precharge prior to beginning the next access. Accordingly, it is desirable for the reference cell and the selected cell to have the same response characteristics because no voltages are truly stationary during high speed accessing. This is achieved by simultaneous accessing and by having matched impedances. Thus, the voltage separation between the reference cell and the selected cell can be maintained even when both are moving even if they are moving in the same direction.

Abstract: Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell. The combination of the first field and the second field is known to saturate a portion, the synthetic antiferromagnet (SAF), of the MRAM cell being written. This can result in not knowing which logic state is ultimately written. This is known to be worsened at higher temperatures. To avoid this deleterious saturation, the magnetic field is reduced during the time when both fields are applied. This is achieved by reducing the current that provides these fields from the current that is applied when only one of the fields is applied.

Abstract: A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in the toggle memory. In one example the toggle memory includes magnetoresistive random access memory (MRAM) with cells using multiple free magnetic layers that toggle between states when subjected to a sequence of magnetic pulses along two directions. Because one read is performed for a group of data of the burst, the time needed to perform the burst write is reduced.

Abstract: A circuit and method of operation compensates for current pulses on a regulated voltage of a voltage supply. The regulated voltage supply is coupled to a plurality of loads that are enabled by a first set of control signals. The enable loads place current pulses having a predetermined plurality on the regulated voltage supply. A second set of control signals enable compensation circuitry to place current pulses of an opposite polarity on the regulated voltage supply. The loads are mimicked to generate a signal that approximates a current pulse length of the enabled loads. Another circuit generates a pulse that approximates a current pulse amplitude of the pulse caused by the enabled loads. By generating compensating pulses of opposite polarity having similar duration and amplitude as the pulses caused by the switching loads, the regulated voltage is more accurately maintained.

Abstract: A computer model simulation for an MRAM cell. In one example, the MRAM cell includes a magnetic tunnel junctions (MTJ) with multiple free magnetic layers. In one embodiment, the simulation implements a state machine whose states variables transition based on indications of magnetic fields passing thresholds. In one embodiment, the conductance values utilized from the model are derived from measured data that is curve fitted to obtain first and second order polynomial coefficient parameters to be used in the model.

Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

Abstract: An embedded memory system (10) uses an MRAM core (12) and error correction code (ECC) corrector circuitry (20). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correctly programmed. The errors are identified and corrected during a read or a write cycle and not necessarily when the memory is in a special test mode. As errors are corrected, the error corrections are counted by an error counter (24) to create a count value. The count value is stored in the MRAM core itself and can later be retrieved and read during a test mode for an indication of how many bit corrections are required for the MRAM core over a period of time. The count value is stored by using an unused portion of a write memory cycle during a read operation.

Abstract: In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) (54) cell is stacked with an asymmetric tunnel device (56). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers (42, 46) separated by an insulator (44). The asymmetric tunnel device (56) is electrically connected in series with the MTJ cell and is formed by at least two conductive layers (48, 52) separated by an insulator (50). The asymmetric tunnel device may be a MIM (56), MIMIM (80) or a MIIM (70). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.

Abstract: A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.

Abstract: A circuit and method for counteracting stray magnetic fields generated by write currents in an MRAM memory reuses the write current in adjoining write columns via a current redistribution bus at a first end of the write lines. A first switch connected to a second end of each write line controls the write current in the write line. If the first switch is not conductive, a second switch connects the second end of the write line to a reference voltage terminal. For write lines located at sub-array edges, a predetermined amount of spacing may be used to avoid magnetic field disturbance in an adjacent sub-array. The number of spaces required can be minimized by specific activation of write line switches.

Abstract: A device for providing fold out fins for stabilizing projectiles or missi which may be tube-launched. The missile is provided with a tubular element or cup which has a plurality of slots defining fin-like stabilizing flaps. The slots extend circumferentially around two sides of the flaps; a third slot interconnects the circumferential slots, while a fourth side is unslotted. Since the tubular element is in fluid communication with the pressure within the launcher, the stabilizing flaps or fins expand outwardly into position about the fourth unslotted side as the missile or the projectile leaves the launcher.