Abstract: Some embodiments include an imaging system. The image sensor array includes multiple image sensor sheets configured in an array grid. Each image sensor sheet of the multiple image sensor sheets can include a flexible substrate layer, and the flexible substrate layer can include a first flexible substrate side and a second flexible substrate side opposite the first flexible substrate side. Meanwhile, each image sensor sheet of the multiple sensor sheets can include multiple image sensors over the first flexible substrate side, the multiple image sensors can include multiple flat panel image detectors configured in a sheet grid, and the image sensor array can include an approximately constant pixel pitch. Other embodiments of related systems and methods are also disclosed.

Abstract: An Indium Tin Oxide (ITO) gate charge coupled device (CCD) is provided. The CCD device comprises a CCD structure having a substrate layer, an oxide layer over the substrate layer, a nitride layer over the oxide layer and a plurality of parallel ITO gates extending over the nitride layer. The CCD device further comprises a plurality of substantially similarly sized channel stop regions in the substrate layer that extend transversely relative to the ITO gates, such that a given pair of channel stop regions defining a pixel column of the CCD structure. The CCD device also comprises a plurality of vent openings that extend through the nitride layer along the plurality of substantially similarly sized channel stop regions to allow for penetration of hydrogen to at least one of the oxide layer and the substrate layer.

Abstract: A high-efficiency lateral multi-junction solar cell (C) includes ultra-low profile planar spectral band splitting micro-optics having a shortpass filter (48) reflecting desired frequencies of light (24) to a reflective mirror (58) combined with spectrally optimized photovoltaic (solar) cells.

Abstract: An Indium Tin Oxide (ITO) gate charge coupled device (CCD) is provided. The CCD device comprises a CCD structure having a substrate layer, an oxide layer over the substrate layer, a nitride layer over the oxide layer and a plurality of parallel ITO gates extending over the nitride layer. The CCD device further comprises a plurality of substantially similarly sized channel stop regions in the substrate layer that extend transversely relative to the ITO gates, such that a given pair of channel stop regions defining a pixel column of the CCD structure. The CCD device also comprises a plurality of vent openings that extend through the nitride layer along the plurality of substantially similarly sized channel stop regions to allow for penetration of hydrogen to at least one of the oxide layer and the substrate layer.

Abstract: One example discloses a heat transfer device that can comprise a semiconductor material having a first region and a second region. The first region and the second region are doped to propel a charged carrier from the first region to the second region. The heat transfer device can also comprise an array of pointed tips thermoelectrically communicating with the second region. A heat sink faces the array, and a vacuum tunneling region is formed between the pointed tips and the heat sink. The heat transfer device further can further comprise a power source for biasing the heat sink with respect to the first region. The first region defines an N-type semiconductor material and the second region defines a P-type semiconductor material.

Abstract: A coiled camera includes a coiling layer, a circuit device layer, active microelectronic circuitry fabricated on the circuit device layer, a semiconductor imaging device electronically coupled to the active microelectronic circuitry and a lens coupled to the semiconductor imaging device.

Abstract: A high-efficiency lateral multi-junction solar cell (C) includes ultra-low profile planar spectral band splitting micro-optics having a shortpass filter (48) reflecting desired frequencies of light (24) to a reflective mirror (58) combined with spectrally optimized photovoltaic (solar) cells.

Abstract: In one embodiment, the disclosure relates to a low-power semiconductor switching device, having a substrate supporting thereon a semiconductor body; a source electrode coupled to the semiconductor body at a source interface region; a drain electrode coupled to the semiconductor body at a drain interface region; a gate oxide film formed over a region of the semiconductor body, the gate oxide film interfacing between a gate electrode and the semiconductor body; wherein at least one of the source interface region or the drain interface region defines a sharp junction into the semiconductor body.

Abstract: The disclosure relates to a Point Cooler based on a combination of principles, including large area, low current density PN junction cooling, and electron emission from heavily doped shallowly-depleted P tips. Using Junction Cooling rather than thermoelectric cooling enables an all silicon device to be made that favorably competes with the commercial thermoelectric cooling systems. Theoretical values of THOT/TCOLD of 6 or more (in contrast to about 1.5 for other solid state refrigerators) predict this single-stage solid state vacuum electronic cooler can approach 50K at light loading, significantly lower than conventional Bismuth Telluride based thermo electrics. The high Z values for PN junction cooling with wire connection and Tunnel heat extraction opens up solid state vibration-less form fit and function replacement cooling.

Abstract: In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+ implant or a blanket P+ implant is disposed in a substrate. A portion of the recessed P+ implant or a portion of the blanket P+ implant is disposed beneath outer edges of the poly-silicon gate, in a channel separating the buried source and the buried drain.

Abstract: An LCD pixel device is provided of the type deployed in a matrix of pixels selectively energized by a plurality of row lines and plurality of column lines and wherein a video voltage is stored on at least one pixel capacitor and coupled to an image-generating device. First and second source regions are formed near the surface of a semiconductor substrate. A drain region is likewise formed in the substrate between the first and second source regions forming the channels of first and second field-effect-transistors. An insulating layer is formed on the substrate, and first and second gate electrodes are provided in the insulating layer between the first source region and the drain region and the second source region and the drain region respectively. First and second mirrors are provided on the surface of the insulating layer.

Abstract: A frame buffer coupled to a LCD pixel comprises a first storage stage and a second storage stage. The frame buffer stores video information to the first storage stage while the second storage stage outputs previously stored video information to the LCD pixel. Video information stored in the first storage stage has a first voltage magnitude. A voltage boost circuit increases the stored video information in the first storage stage to a second voltage magnitude when the second storage stage is coupled for receiving video information from the first stage. The video information of the second voltage magnitude is converted and stored in the second storage stage having the first voltage magnitude.

Abstract: An LCD pixel device is provided of the type deployed in a matrix of pixels selectively energized by a plurality of row lines and plurality of column lines and wherein a video voltage is stored on at least one pixel capacitor and coupled to an image-generating device. First and second source regions are formed near the surface of a semiconductor substrate. A drain region is likewise formed in the substrate between the first and second source regions forming the channels of first and second field-effect-transistors. An insulating layer is formed on the substrate, and first and second gate electrodes are provided in the insulating layer between the first source region and the drain region and the second source region and the drain region respectively. First and second mirrors are provided on the surface of the insulating layer.

Abstract: An LCD micro display for generating an image of a video signal includes a matrix of pixels arranged in a plurality of rows and a plurality of columns, which are selectively energized to create the image. The rows are connected to a row select circuit for energizing each of the rows in accordance with a first predetermined sequence. The columns are coupled to a column select circuit coupling the video signal to each of the columns in accordance with the second predetermined sequence. The column select circuit includes a plurality of video switches, each of which include a high speed current mirror level shifter for shifting the control signal from a first potential to a second higher potential. A transmission gate couples the video signal to one of the columns upon receipt of the higher potential control signal.

Abstract: An LCD pixel device is provided of the type deployed in a matrix of pixels selectively energized by a plurality of row lines and plurality of column lines and wherein a video voltage is stored on at least one pixel capacitor and coupled to an image-generating device. First and second source regions are formed near the surface of a semiconductor substrate. A drain region is likewise formed in the substrate between the first and second source regions forming the channels of first and second field-effect-transistors. An insulating layer is formed on the substrate, and first and second gate electrodes are provided in the insulating layer between the first source region and the drain region and the second source region and the drain region respectively. First and second mirrors are provided on the surface of the insulating layer.

Abstract: A row driver circuit applies a boosted access voltage to a selected row of an LCD matrix so as to permit a higher video voltage to be stored on the pixel capacitor. The row driver circuit includes an input stage that operates at a first potential for receiving at least first and second control signals. The output of the input stage is coupled to a level shifting stage that operates at a second higher operating potential. The output of the level shifting stage is coupled to an output stage that generates a boosted access voltage having a potential that is higher than the operating potential of the level shifting stage.

Abstract: An LCD micro display for generating an image of a video signal includes a matrix of pixels arranged in a plurality of rows and a plurality of columns, which are selectively energized to create the image. The rows are connected to a row select circuit for energizing each of the rows in accordance with a first predetermined sequence. The columns are coupled to a column select circuit coupling the video signal to each of the columns in accordance with the second predetermined sequence. The column select circuit includes a plurality of video switches, each of which include a high speed current mirror level shifter for shifting the control signal from a first potential to a second higher potential. A transmission gate couples the video signal to one of the columns upon receipt of the higher potential control signal.