Patents by Inventor Josephine Chang
Josephine Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230307533Abstract: A field effect transistor, comprising: a substrate and a superlattice of stacked conducting channels on the substrate; a source and a drain spaced-apart from each other on the superlattice; alternating castellations and trenches formed in the superlattice between the source and the drain, wherein the castellations have sidewalls that cut-down through the superlattice to form the trenches and edges of the stacked conducting channels that terminate at the sidewalls; a fringe field dielectric that fills lower volumes of the trenches up to a height on the sidewalls that is higher than first edges of first conducting channels among the stacked conducting channels, such that the fringe field dielectric is adjacent to the first edges; and a gate electrode overlaying the fringe field dielectric and the castellations such that the gate electrode is not adjacent to the first edges.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Inventors: Kevin M. Frey, Ken Nagamatsu, Josephine Chang, Robert S. Howell
-
Publication number: 20220093772Abstract: A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Josephine Chang, Isaac Lauer, Jeffrey Sleight
-
Publication number: 20200411676Abstract: An enhancement-mode (e-mode) field effect transistor (FET) comprises a buffer layer, and a superlattice of conducting channels on the buffer layer and including a trench that cuts down through the superlattice into the buffer layer and separates the superlattice into a source-access region and a drain-access region, wherein the buffer layer forms a bottom of the trench. The e-mode FET includes a source and a drain adjacent to the source-access region and the drain-access region, respectively. The e-mode FET further incudes a gate in the trench, such that a voltage above a threshold voltage of the e-mode FET applied to the gate induces a current channel in the buffer layer underneath the gate, which electrically connects the source-access region to the drain-access region to turn on the e-mode FET, and (ii) a voltage below the threshold voltage applied to the gate eliminates the current channel, which electrically disconnects the source-access region from the drain-access region to turn off the e-mode FET.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Inventors: Josephine Chang, Ken Nagamatsu, Robert S. Howell, Sarat Saluru
-
Patent number: 10879382Abstract: An enhancement-mode (e-mode) field effect transistor (FET) comprises a buffer layer, and a superlattice of conducting channels on the buffer layer and including a trench that cuts down through the superlattice into the buffer layer and separates the superlattice into a source-access region and a drain-access region, wherein the buffer layer forms a bottom of the trench. The e-mode FET includes a source and a drain adjacent to the source-access region and the drain-access region, respectively. The e-mode FET further includes a gate in the trench, such that a voltage above a threshold voltage of the e-mode FET applied to the gate induces a current channel in the buffer layer underneath the gate, which electrically connects the source-access region to the drain-access region to turn on the e-mode FET, and (ii) a voltage below the threshold voltage applied to the gate eliminates the current channel, which electrically disconnects the source-access region from the drain-access region to turn off the e-mode FET.Type: GrantFiled: June 26, 2019Date of Patent: December 29, 2020Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Josephine Chang, Ken Nagamatsu, Robert S. Howell, Sarat Saluru
-
Patent number: 10325982Abstract: A transistor device comprises a base structure and a superlattice of conducting channels overlying the base structure. The superlattice of conducting channels includes source and drain access regions spaced-apart from each other, a ledge between and spaced-apart from the source and drain access regions, and source-side alternating multichannel ridges and trenches that extend from the source access region to the ledge, each ridge having a topside and opposing sidewalls that each extend from the ledge to the source access region. The transistor device includes gate metal that covers each ridge continuously from the ledge to the source access region, such that the gate metal completely covers the topside of the ridge and edges of the conducting channels that intersect the sidewalls of the ridge.Type: GrantFiled: May 17, 2018Date of Patent: June 18, 2019Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Josephine Chang, Ken Alfred Nagamatsu, Robert Samuel Howell, Shalini Gupta
-
Patent number: 9368599Abstract: A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.Type: GrantFiled: June 22, 2010Date of Patent: June 14, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine Chang, Isaac Lauer, Jeffrey Sleight
-
Patent number: 9281397Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.Type: GrantFiled: January 17, 2014Date of Patent: March 8, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Josephine Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey Sleight
-
Patent number: 8877593Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.Type: GrantFiled: July 31, 2011Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Josephine Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey Sleight
-
Patent number: 8766410Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.Type: GrantFiled: June 6, 2011Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
-
Publication number: 20140131708Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.Type: ApplicationFiled: January 17, 2014Publication date: May 15, 2014Applicant: International Business Machines CorporationInventors: Josephine Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey Sleight
-
Publication number: 20130309837Abstract: Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins.Type: ApplicationFiled: May 15, 2012Publication date: November 21, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JOSEPHINE CHANG, MICHAEL A. GUILLORN, BALASUBRAMANIAN PRANATHARTHIHARAN, JEFFREY WILLIAM SLEIGHT
-
Patent number: 8586455Abstract: Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins.Type: GrantFiled: May 15, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Josephine Chang, Michael A. Guillorn, Balasubramanian Pranatharthiharan, Jeffrey William Sleight
-
Patent number: 8472239Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.Type: GrantFiled: May 9, 2012Date of Patent: June 25, 2013Assignee: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
-
Patent number: 8466451Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.Type: GrantFiled: December 11, 2011Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
-
Patent number: 8422273Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.Type: GrantFiled: May 21, 2009Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
-
Patent number: 8395220Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.Type: GrantFiled: March 12, 2012Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
-
Publication number: 20130026465Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.Type: ApplicationFiled: July 31, 2011Publication date: January 31, 2013Applicant: International Business Machines CorporationInventors: Josephine Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey Sleight
-
Publication number: 20120298949Abstract: A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine Chang, Isaac Lauer, Jeffrey Sleight
-
Publication number: 20120217479Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: Internatiional Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
-
Patent number: 8216902Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.Type: GrantFiled: August 6, 2009Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight