Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract: Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.

Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: An ultraviolet (UV) cure chamber enables curing a dielectric material disposed on a substrate and in situ cleaning thereof. A tandem process chamber provides two separate and adjacent process regions defined by a body covered with a lid having windows aligned respectively above each process region. One or more UV bulbs per process region that are covered by housings coupled to the lid emit UV light directed through the windows onto substrates located within the process regions. The UV bulbs can be an array of light emitting diodes or bulbs utilizing a source such as microwave or radio frequency. The UV light can be pulsed during a cure process. Using oxygen radical/ozone generated remotely and/or in-situ accomplishes cleaning of the chamber. Use of lamp arrays, relative motion of the substrate and lamp head, and real-time modification of lamp reflector shape and/or position can enhance uniformity of substrate illumination.

Abstract: An ultraviolet (UV) cure chamber enables curing a dielectric material disposed on a substrate and in situ cleaning thereof. A tandem process chamber provides two separate and adjacent process regions defined by a body covered with a lid having windows aligned respectively above each process region. One or more UV sources per process region that are covered by housings coupled to the lid emit UV light directed through the windows onto substrates located within the process regions. The UV sources can be an array of light emitting diodes or bulbs utilizing a source such as microwave or radio frequency. The UV light can be pulsed during a cure process. Using oxygen radical/ozone generated remotely and/or in-situ accomplishes cleaning of the chamber. Use of lamp arrays, relative motion of the substrate and lamp head, and real-time modification of lamp reflector shape and/or position can enhance uniformity of substrate illumination.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: An ultraviolet (UV) cure chamber enables curing a dielectric material disposed on a substrate and in situ cleaning thereof. A tandem process chamber provides two separate and adjacent process regions defined by a body covered with a lid having windows aligned respectively above each process region. One or more UV bulbs per process region that are covered by housings coupled to the lid emit UV light directed through the windows onto substrates located within the process regions. The UV bulbs can be an array of light emitting diodes or bulbs utilizing a source such as microwave or radio frequency. The UV light can be pulsed during a cure process. Using oxygen radical/ozone generated remotely and/or in-situ accomplishes cleaning of the chamber. Use of lamp arrays, relative motion of the substrate and lamp head, and real-time modification of lamp reflector shape and/or position can enhance uniformity of substrate illumination.

Abstract: An ultraviolet (UV) cure chamber enables curing a dielectric material disposed on a substrate and in situ cleaning thereof. A tandem process chamber provides two separate and adjacent process regions defined by a body covered with a lid having windows aligned respectively above each process region. One or more UV bulbs per process region that are covered by housings coupled to the lid emit UV light directed through the windows onto substrates located within the process regions. The UV bulbs can be an array of light emitting diodes or bulbs utilizing a source such as microwave or radio frequency. The UV light can be pulsed during a cure process. Using oxygen radical/ozone generated remotely and/or in-situ accomplishes cleaning of the chamber. Use of lamp arrays, relative motion of the substrate and lamp head, and real-time modification of lamp reflector shape and/or position can enhance uniformity of substrate illumination.

Abstract: An ultraviolet (UV) cure chamber enables curing a dielectric material disposed on a substrate and in situ cleaning thereof. A tandem process chamber provides two separate and adjacent process regions defined by a body covered with a lid having windows aligned respectively above each process region. One or more UV bulbs per process region that are covered by housings coupled to the lid emit UV light directed through the windows onto substrates located within the process regions. The UV bulbs can be an array of light emitting diodes or bulbs utilizing a source such as microwave or radio frequency. The UV light can be pulsed during a cure process. Using oxygen radical/ozone generated remotely and/or in-situ accomplishes cleaning of the chamber. Use of lamp arrays, relative motion of the substrate and lamp head, and real-time modification of lamp reflector shape and/or position can enhance uniformity of substrate illumination.

Abstract: A method of depositing a low dielectric constant film on a substrate and post-treating the low dielectric constant film is provided. The post-treatment includes rapidly heating the low dielectric constant film to a desired high temperature and then rapidly cooling the low dielectric constant film such that the low dielectric constant film is exposed to the desired high temperature for about five seconds or less. In one aspect, the post-treatment also includes exposing the low dielectric constant film to an electron beam treatment and/or UV radiation.

Abstract: A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.

Abstract: A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.

Abstract: An accurate speech recognition system capable of rapidly processing greater varieties of words and operable in many different devices, but without the computational power and memory requirements, high power consumption, complex operating system, high costs, and weight of traditional systems. The utilization of individual letter utterances to transmit words allows voice information transfer for both person-to-person and person-to-machine communication for mobile phones, PDAs, and other communication devices.