Patents by Inventor Joshua Barczak
Joshua Barczak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220051476Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.Type: ApplicationFiled: December 23, 2020Publication date: February 17, 2022Inventors: Sven Woop, Michael J. Doyle, Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Carsten Benthin, Prasoonkumar Surti, Holger GRUEN, Stephen Junkins, Adam Lake, Bret G. Alfieri, Gabor Liktor, Joshua Barczak, Won-Jong Lee
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Patent number: 11158111Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.Type: GrantFiled: June 29, 2020Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Kai Xiao, Michael Apodaca, Carson Brownlee, Thomas Raoux, Joshua Barczak, Gabor Liktor
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Publication number: 20210327120Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.Type: ApplicationFiled: May 5, 2021Publication date: October 21, 2021Applicant: Intel CorporationInventors: CARSON BROWNLEE, GABOR LIKTOR, JOSHUA BARCZAK, KAI XIAO, MICHAEL APODACA, THOMAS RAOUX
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Patent number: 11069123Abstract: Cloud-based real time rendering.Type: GrantFiled: December 28, 2018Date of Patent: July 20, 2021Assignee: INTEL CORPORATIONInventors: Carson Brownlee, Joshua Barczak, Kai Xiao, Michael Apodaca, Philip Laws, Thomas Raoux, Travis Schluessler
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Patent number: 11004252Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.Type: GrantFiled: December 28, 2018Date of Patent: May 11, 2021Assignee: Intel CorporationInventors: Carson Brownlee, Gabor Liktor, Joshua Barczak, Kai Xiao, Michael Apodaca, Thomas Raoux
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Publication number: 20210097750Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Sven Woop, Prasoonkumar Surti, Karthik Vaidyanathan, Carsten Benthin, Joshua Barczak, Saikat Mandal
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Publication number: 20210082154Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.Type: ApplicationFiled: August 26, 2020Publication date: March 18, 2021Inventors: Carson BROWNLEE, Carsten BENTHIN, Joshua BARCZAK, Kai XIAO, Michael APODACA, Prasoonkumar SURTI, Thomas RAOUX
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Publication number: 20210042987Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Karthik VAIDYANATHAN, Michael APODACA, Thomas RAOUX, Carsten BENTHIN, Kai XIAO, Carson BROWNLEE, Joshua BARCZAK
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Publication number: 20210035349Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.Type: ApplicationFiled: August 18, 2020Publication date: February 4, 2021Inventors: Karthik VAIDYANATHAN, Michael APODACA, Thomas RAOUX, Carsten BENTHIN, Kai XIAO, Carson BROWNLEE, Joshua BARCZAK
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Publication number: 20210012553Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Inventors: Michael APODACA, Carsten BENTHIN, Kai XIAO, Carson BROWNLEE, Timothy ROWLEY, Joshua BARCZAK, Travis SCHLUESSLER
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Publication number: 20200402291Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.Type: ApplicationFiled: June 29, 2020Publication date: December 24, 2020Applicant: Intel CorporationInventors: KAI XIAO, MICHAEL APODACA, CARSON BROWNLEE, THOMAS RAOUX, JOSHUA BARCZAK, GABOR LIKTOR
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Patent number: 10762668Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.Type: GrantFiled: December 28, 2018Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Carson Brownlee, Carsten Benthin, Joshua Barczak, Kai Xiao, Michael Apodaca, Prasoonkumar Surti, Thomas Raoux
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Patent number: 10755469Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.Type: GrantFiled: December 28, 2018Date of Patent: August 25, 2020Assignee: Intel CorporationInventors: Karthik Vaidyanathan, Michael Apodaca, Thomas Raoux, Carsten Benthin, Kai Xiao, Carson Brownlee, Joshua Barczak
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Patent number: 10740953Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.Type: GrantFiled: December 28, 2018Date of Patent: August 11, 2020Assignee: Intel CorporationInventors: Kai Xiao, Michael Apodaca, Carson Brownlee, Thomas Raoux, Joshua Barczak, Gabor Liktor
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Publication number: 20200211266Abstract: Real time ray tracing-based adaptive multi frequency shading. For example, one embodiment of an apparatus comprising: rasterization hardware logic to process input data for an image in a deferred rendering pass and to responsively update one or more graphics buffers with first data to be used in a subsequent rendering pass; ray tracing hardware logic to perform ray tracing operations using the first data to generate reflection ray data and to store the reflection ray data in a reflection buffer; and image rendering circuitry to perform texture sampling in a texture buffer based on the reflection ray data in the reflection buffer to render an output image.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: CARSON BROWNLEE, GABOR LIKTOR, JOSHUA BARCZAK, KAI XIAO, MICHAEL APODACA, THOMAS RAOUX
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Publication number: 20200211259Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: MICHAEL APODACA, CARSTEN BENTHIN, KAI XIAO, CARSON BROWNLEE, TIMOTHY ROWLEY, JOSHUA BARCZAK, TRAVIS SCHLUESSLER
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Publication number: 20200211265Abstract: Cloud-based real time rendering.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Carson BROWNLEE, Joshua BARCZAK, Kai XIAO, Michael APODACA, Philip LAWS, Thomas RAOUX, Travis SCHLUESSLER
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Publication number: 20200211231Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: CARSON BROWNLEE, CARSTEN BENTHIN, JOSHUA BARCZAK, KAI XIAO, MICHAEL APODACA, PRASOONKUMAR SURTI, THOMAS RAOUX
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Publication number: 20200211262Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: KARTHIK VAIDYANATHAN, MICHAEL APODACA, THOMAS RAOUX, CARSTEN BENTHIN, KAI XIAO, CARSON BROWNLEE, JOSHUA BARCZAK
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Publication number: 20200211260Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: KAI XIAO, MICHAEL APODACA, CARSON BROWNLEE, THOMAS RAOUX, JOSHUA BARCZAK, GABOR LIKTOR