Patents by Inventor Joshua Haeseok Cho
Joshua Haeseok Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10476460Abstract: Low-noise amplifier having programmable-phase gain stage. In some embodiments, a radio-frequency amplifier can include an input node, an output node, and a programmable-phase gain stage implemented between the input node and the output node. The programmable-phase gain stage can be configured to operate in one of a plurality of gain settings, and to provide a desired phase for a signal at each of the plurality of gain settings.Type: GrantFiled: August 28, 2017Date of Patent: November 12, 2019Assignee: Skyworks Solutions, Inc.Inventors: Junhyung Lee, Johannes Jacobus Emile Maria Hageraats, Joshua Haeseok Cho
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Patent number: 10389305Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers can also have switchable reference biases to provide targeted bias current matching. The disclosed signal amplifiers can also include degeneration switching blocks for individual amplifier cores to improve signal linearity.Type: GrantFiled: December 20, 2017Date of Patent: August 20, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Junhyung Lee, Johannes Jacobus Emile Maria Hageraats, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
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Patent number: 10348262Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths that allow signals in a high gain mode to bypass attenuation. This advantageously reduces or eliminates performance penalties in the high gain mode. The programmable attenuators can be configured to improve linearity of the amplification process through pre-LNA attenuation in targeted gain modes. In addition, described herein are variable gain amplifiers with embedded attenuators in a switching network. The attenuators can be embedded onto switches and can be configured to have little or no effect on a noise factor in a high gain mode because the switching network can provide an attenuation bypass in a high gain mode and an attenuation in other gain modes. The programmable attenuators can be embedded onto a multi-input LNA architecture.Type: GrantFiled: August 30, 2017Date of Patent: July 9, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Junhyung Lee, Rimal Deep Singh, Johannes Jacobus Emile Maria Hageraats, Joshua Haeseok Cho, Bipul Agarwal, Aravind Kumar Padyana
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Publication number: 20190207639Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. The degeneration block can be selectively isolated from a reference potential node to improve performance.Type: ApplicationFiled: March 12, 2019Publication date: July 4, 2019Inventors: Johannes Jacobus Emile Maria Hageraats, Junhyung Lee, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
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Patent number: 10230417Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.Type: GrantFiled: August 30, 2017Date of Patent: March 12, 2019Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Johannes Jacobus Emile Maria Hageraats, Junhyung Lee, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
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Patent number: 10056880Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.Type: GrantFiled: August 16, 2017Date of Patent: August 21, 2018Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Publication number: 20180175797Abstract: Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers can also have switchable reference biases to provide targeted bias current matching. The disclosed signal amplifiers can also include degeneration switching blocks for individual amplifier cores to improve signal linearity.Type: ApplicationFiled: December 20, 2017Publication date: June 21, 2018Inventors: Junhyung Lee, Johannes Jacobus Emile Maria Hageraats, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
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Publication number: 20180062600Abstract: Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths that allow signals in a high gain mode to bypass attenuation. This advantageously reduces or eliminates performance penalties in the high gain mode. The programmable attenuators can be configured to improve linearity of the amplification process through pre-LNA attenuation in targeted gain modes. In addition, described herein are variable gain amplifiers with embedded attenuators in a switching network. The attenuators can be embedded onto switches and can be configured to have little or no effect on a noise factor in a high gain mode because the switching network can provide an attenuation bypass in a high gain mode and an attenuation in other gain modes. The programmable attenuators can be embedded onto a multi-input LNA architecture.Type: ApplicationFiled: August 30, 2017Publication date: March 1, 2018Inventors: Junhyung LEE, Rimal Deep Singh, Johannes Jacobus Emile Maria Hageraats, Joshua Haeseok Cho, Bipul Agarwal, Aravind Kumar Padyana
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Publication number: 20180062690Abstract: Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.Type: ApplicationFiled: August 30, 2017Publication date: March 1, 2018Inventors: Johannes Jacobus Emile Maria Hageraats, Junhyung Lee, Joshua Haeseok Cho, Aravind Kumar Padyana, Bipul Agarwal
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Publication number: 20180062599Abstract: Low-noise amplifier having programmable-phase gain stage. In some embodiments, a radio-frequency amplifier can include an input node, an output node, and a programmable-phase gain stage implemented between the input node and the output node. The programmable-phase gain stage can be configured to operate in one of a plurality of gain settings, and to provide a desired phase for a signal at each of the plurality of gain settings.Type: ApplicationFiled: August 28, 2017Publication date: March 1, 2018Inventors: Junhyung LEE, Johannes Jacobus Emile Maria HAGERAATS, Joshua Haeseok CHO
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Publication number: 20180034445Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.Type: ApplicationFiled: August 16, 2017Publication date: February 1, 2018Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Patent number: 9866202Abstract: Digitally controlled attenuators with low phase shift are provided herein. In certain configurations, a digitally controlled attenuator includes an attenuation circuit electrically connected between an input terminal and an output terminal, a bypass circuit electrically connected in parallel with the attenuation circuit between the input terminal and the output terminal, and a plurality of phase compensation capacitors including a first phase compensation capacitor and a second phase compensation capacitor electrically connected in series between the input terminal and the output terminal. The bypass circuit is configured to receive a mode control signal for selecting the bypass circuit to control an amount of attenuation between the input terminal and the output terminal. Additionally, the phase compensation capacitors are operable to compensate for a phase difference between a first signal path through the attenuation circuit and a second signal path through the bypass circuit.Type: GrantFiled: January 18, 2017Date of Patent: January 9, 2018Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Patent number: 9787285Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.Type: GrantFiled: September 14, 2016Date of Patent: October 10, 2017Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Publication number: 20170126208Abstract: Digitally controlled attenuators with low phase shift are provided herein. In certain configurations, a digitally controlled attenuator includes an attenuation circuit electrically connected between an input terminal and an output terminal, a bypass circuit electrically connected in parallel with the attenuation circuit between the input terminal and the output terminal, and a plurality of phase compensation capacitors including a first phase compensation capacitor and a second phase compensation capacitor electrically connected in series between the input terminal and the output terminal. The bypass circuit is configured to receive a mode control signal for selecting the bypass circuit to control an amount of attenuation between the input terminal and the output terminal. Additionally, the phase compensation capacitors are operable to compensate for a phase difference between a first signal path through the attenuation circuit and a second signal path through the bypass circuit.Type: ApplicationFiled: January 18, 2017Publication date: May 4, 2017Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Patent number: 9584096Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a digital step attenuator (DSA) includes a plurality of DSA stages arranged in a cascade between an input terminal and an output terminal. Each of the DSA stages can be operated in an attenuation mode or in a bypass mode. The DSA further includes an attenuation control circuit, which can be used to control the modes of operation of the DSA stages. The attenuation control circuit can be used to operate the DSA over a plurality of attenuation steps, which can be digitally selectable. To provide low phase shift across the range of attenuation steps, a DSA stage can include one or more phase compensation capacitors used to provide low phase shift and to compensate for a phase difference between the DSA stage operating in the bypass mode and in the attenuation mode.Type: GrantFiled: May 5, 2015Date of Patent: February 28, 2017Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Publication number: 20170033771Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.Type: ApplicationFiled: September 14, 2016Publication date: February 2, 2017Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Patent number: 9473109Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.Type: GrantFiled: May 5, 2015Date of Patent: October 18, 2016Assignee: SKYWORKS SOLUTIONS, INC.Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Publication number: 20150326205Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a digital step attenuator (DSA) includes a plurality of DSA stages arranged in a cascade between an input terminal and an output terminal. Each of the DSA stages can be operated in an attenuation mode or in a bypass mode. The DSA further includes an attenuation control circuit, which can be used to control the modes of operation of the DSA stages. The attenuation control circuit can be used to operate the DSA over a plurality of attenuation steps, which can be digitally selectable. To provide low phase shift across the range of attenuation steps, a DSA stage can include one or more phase compensation capacitors used to provide low phase shift and to compensate for a phase difference between the DSA stage operating in the bypass mode and in the attenuation mode.Type: ApplicationFiled: May 5, 2015Publication date: November 12, 2015Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal
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Publication number: 20150326204Abstract: Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.Type: ApplicationFiled: May 5, 2015Publication date: November 12, 2015Inventors: Joshua Haeseok Cho, Yunyoung Choi, Bipul Agarwal