Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Abstract: A system includes a plurality of oscilloscopes, each oscilloscope having an output port and an input port, a cable connecting the output port of an initial oscilloscope of the plurality of oscilloscopes to the input port of a second oscilloscope of the plurality of oscilloscopes, the initial oscilloscope having a processing element to generate a master run clock, the second oscilloscope having a processing element including a phase-locked loop to lock a slave run clock to the master run clock, wherein the processing element of one of the oscilloscopes executes code to cause the processing element to manipulate one of the run clocks to pass trigger information to another of the plurality of oscilloscopes.

Abstract: A test and measurement device includes an input port for receiving a bus conducting data from a device under test, and processing element coupled to the input port. The processing element is configured to execute instructions that cause the processing element to determine a data sequence from a signal of the bus received on a main channel of the device, and use information from at least one other signal of the bus on an auxiliary channel of the device based upon a protocol associated with the bus to adjust parameters for performing error detection on the data sequence.

Abstract: A system includes a plurality of oscilloscopes, each oscilloscope having an output port and an input port, a cable connecting the output port of an initial oscilloscope of the plurality of oscilloscopes to the input port of a second oscilloscope of the plurality of oscilloscopes, the initial oscilloscope having a processing element to generate a master run clock, the second oscilloscope having a processing element including a phase-locked loop to lock a slave run clock to the master run clock, wherein the processing element of one of the oscilloscopes executes code to cause the processing element to manipulate one of the run clocks to pass trigger information to another of the plurality of oscilloscopes.

Abstract: A system includes a plurality of oscilloscopes, each oscilloscope having an output port and an input port, a cable connecting the output port of an initial oscilloscope of the plurality of oscilloscopes to the input port of a second oscilloscope of the plurality of oscilloscopes, the initial oscilloscope having a processing element to generate a master run clock, the second oscilloscope having a processing element including a phase-locked loop to lock a slave run clock to the master run clock, wherein the processing element of one of the oscilloscopes executes code to cause the processing element to manipulate one of the run clocks to pass trigger information to another of the plurality of oscilloscopes.

Abstract: A test and measurement system can include a data store configured to store augmentation settings for dynamically augmenting a physical testing environment and a computing device coupled to the data store. The computing device can be configured to receive an input feed from the physical testing environment, create an augmentation image based on the augmentation settings and the input feed, and output the augmented image to be overlaid on the physical testing environment to augment a user's view of the physical testing environment.

Abstract: A test and measurement instrument can include an input to receive an analog signal, a sampler to produce digital sample data corresponding to the analog signal, a buffer to store a portion of the sample data, a memory to store sample data from the buffer, a plurality of comparators to establish a vertical range, and a controller configured to configure the plurality of comparators to establish a first vertical range based on sample data in the buffer, and determine whether any of the sample data in the buffer transitions outside the first vertical range during a period of time.

Abstract: A method of classifying waveform data includes receiving input waveform data at a test and measurement system, accessing a repository of reference waveform data and corresponding classes, analyzing the input waveform data and the reference waveform data to designate a class of the input waveform data, and using the class designation to provide information to a user. A test and measurement system has a user interface, at least one input port, a communications port, a processor, the processor configured to execute instructions causing the processor to: receive input waveform data through at least one of the input port or the user interface; access a repository of reference waveform data; analyze the input waveform data using the reference waveform data; designate a class of the input waveform data; and use the class to provide information to the user about the input waveform.

Abstract: A test and measurement instrument can include an input to receive an analog signal, a sampler to produce digital sample data corresponding to the analog signal, a buffer to store a portion of the sample data, a memory to store sample data from the buffer, a plurality of comparators to establish a vertical range, and a controller configured to configure the plurality of comparators to establish a first vertical range based on sample data in the buffer, and determine whether any of the sample data in the buffer transitions outside the first vertical range during a period of time.

Abstract: The slot interposer probe consists of a board with a male edge connector and a female edge connector connected to its opposed edges and circuitry electrically connecting the male edge connector to the female edge connector. The female edge connector may be a straddle-mount connector. The board may have an inner layer sandwiched between two outer layers. There may be a probe having a high-speed buffer connected to a plurality of capacitors, isolation resistors, and vias that intercepts signals carried by transmission lines on the inner layer. The vias may have a length equal to the inner layer's width. The high-speed buffer receives intercepted signals from the vias, copies and amplifies the signals, and drives them through coaxial cables to an acquisition module. The invention also includes a method of intercepting signals between a first electrical device and a second electrical device.

Abstract: The slot interposer probe consists of a board with a male edge connector and a female edge connector connected to its opposed edges and circuitry electrically connecting the male edge connector to the female edge connector. The female edge connector may be a straddle-mount connector. The board may have an inner layer sandwiched between two outer layers. There may be a probe having a high-speed buffer connected to a plurality of capacitors, isolation resistors, and vias that intercepts signals carried by transmission lines on the inner layer. The vias may have a length equal to the inner layer's width. The high-speed buffer receives intercepted signals from the vias, copies and amplifies the signals, and drives them through coaxial cables to an acquisition module. The invention also includes a method of intercepting signals between a first electrical device and a second electrical device.