Abstract: A multimode pixel of a pixel array is provided. The multimode pixel includes a photodetector, an image sensing circuit, a pulse detection circuit, and an image readout path coupled between the image sensing circuit and at least one readout conductor of the pixel array to transmit image signals from the image sensing circuit to the at least one readout conductor. The multimode pixel further includes a pulse readout path different from the image readout path, wherein the pulse readout path is coupled between the pulse detection circuit and the at least one readout conductor to transmit pulse data from the pulse detection circuit to the at least one readout conductor, and wherein the image readout path is controlled independently from the pulse readout path.

Abstract: An imaging pixel including a control device to control flow of a charge signal from a photodetector. The control device has a variable impedance that varies in response to frequency of an input signal, the control device being biased to permit signals to flow through the control device dependent on the frequency of signals being output by the photodetector. The imaging pixel further includes a low-frequency signal path that receives a flow of signals that flow through the control device, and a high-frequency signal path independent of the low-frequency signal path and the control device, the high-frequency signal path receiving high-frequency signals included in the charge signal.

Abstract: A leakage mitigation circuit is provided. The leakage mitigation circuit includes an inverter coupled to a storage node, wherein the storage node receives a signal output by an imaging pixel having a first voltage level to be stored. The inverter inverts the signal to a second voltage level. A single transistor coupled to the inverter and the storage node inverts the signal output by the inverter to the first level to hold the signal at the storage node to its original level. A self-biased device coupled to the inverter lowers current disturbance related to the storage node and increase threshold voltage at which fluctuation of the level of the signal at the storage node causes the signal to be inverted by the inverter.

Abstract: A photosensitive pixel with gain stage is disclosed. The photosensitive pixel with gain stage may receive an input light stimulus and output a corresponding output voltage in response to the input light stimulus. The output voltage may correspond linearly to the magnitude of the input light stimulus over a linear operating region and logarithmically to the magnitude of the input light stimulus over a logarithmic operating region. In this manner, the photosensitive pixel with gain stage may be both sensitive to input light stimuli over the linear operating region and may exhibit dynamic range enabling non-saturated response to input light stimuli over the logarithmic operating region.

Abstract: An imaging pixel is provided. The imaging pixel includes a photodetector that outputs charge signals in response to incident light and laser pulses and a high-frequency path. A detector biasing circuit is further provided that biases high-frequency signals of the charge signals that are associated with the laser pulses to follow the high frequency path. The detector biasing circuit effectively filters low-frequency signal components of the charge signals from following the high-frequency path.

Abstract: A pixel master-slave photodiode bias control amplifier system is disclosed. The pixel master-slave photodiode bias control amplifier system may include a master pixel and one or more slave pixels. The slave pixel(s) may be connected to a portion of the master pixel. In this manner, components may be shared between/among the master pixel and the slave pixel(s); thus, for example, optimizing the component count of the pixel master-slave photodiode bias control amplifier system and the size occupied by the pixel master-slave photodiode bias control amplifier system.

Abstract: An imaging pixel including a control device to control flow of a charge signal from a photodetector. The control device has a variable impedance that varies in response to frequency of an input signal, the control device being biased to permit signals to flow through the control device dependent on the frequency of signals being output by the photodetector. The imaging pixel further includes a low-frequency signal path that receives a flow of signals that flow through the control device, and a high-frequency signal path independent of the low-pass filter and the control device, the high-frequency signal path receiving high-frequency signals included in the charge signal.

Abstract: An imaging pixel is provided. The imaging pixel includes a photodetector that outputs charge signals in response to incident light and laser pulses and a high-frequency path. A detector biasing circuit is further provided that biases high-frequency signals of the charge signals that are associated with the laser pulses to follow the high frequency path. The detector biasing circuit effectively filters low-frequency signal components of the charge signals from following the high-frequency path.

Abstract: A wavefront sensing pixel is provided. The wavefront sensing pixel includes a low-pass filter filtering a charge signal from a photodetector and outputting a control signal when low-frequency signals are detected in the charge signal, and a control device to control flow of the charge signal past the control device based on whether a low-frequency signal is detected in the charge signal. The wavefront sensing pixel further includes a low-frequency signal path that receives a flow of signals that flow past the control device, and a high-frequency signal path independent of the low-pass filter and the control device, the high-frequency signal path receiving high-frequency signals included in the charge signal.

Abstract: A leakage mitigation circuit is provided. The leakage mitigation circuit includes an inverter coupled to a storage node, wherein the storage node receives a signal output by an imaging pixel having a first voltage level to be stored. The inverter inverts the signal to a second voltage level. A single transistor coupled to the inverter and the storage node inverts the signal output by the inverter to the first level to hold the signal at the storage node to its original level. A self-biased device coupled to the inverter lowers current disturbance related to the storage node and increase threshold voltage at which fluctuation of the level of the signal at the storage node causes the signal to be inverted by the inverter.

Abstract: An imaging and pulse detection (IPD) pixel array includes a plurality of imaging pixels arranged in a plurality of rows and columns. Each imaging pixel includes a respective photodetector that outputs signals in response to incident light and input laser pulses. The signals include imaging signals that correspond to the incident light and pulse signals that correspond to the input laser pulses. The IPD array further includes an isolation circuit associated with each of the respective imaging pixels, each isolation circuit outputting filtered output pulse signals in response to receiving the signals from the associated imaging pixel, the filtered output pulse signals corresponding to the pulse signals. The IPD array further includes a single pulse detection circuit that toggles between a charged and uncharged state corresponding to a pulse being received from at least one of the isolation circuits.

Abstract: An imaging and pulse detection array includes: a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in the plurality of pixels and configured to detect a pulse on at least one of the pixels in the plurality of pixels, and each of the pixels in the plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein the imaging circuit and the pulse detection circuit include a shared portion.

Abstract: A pixel cell includes a first integration capacitor, a second integration capacitor, a photo detector and a transistor. The first integration capacitor includes a first lead operatively coupled to the photo detector. The second integration capacitor includes a first lead. The transistor is operatively coupled between the leads of the first and second integration capacitors for enabling current flow between the photo detector and the second integration capacitor only once a threshold voltage is met on the first integration capacitor.

Abstract: A pulse detecting imaging circuit includes a pixel array including multiple pixels arranged in at least one row and at least one column. The pixel array includes multiple row voltages and column voltages. Each of the row voltages is connected to each pixel in the corresponding row and each of the column voltages is connected to each pixel in the corresponding column. Each of said pixels includes an imaging circuit and a pulse detection circuit. An output of each pulse detection circuit is connected to a corresponding row voltage and a corresponding column voltage such that each pixel is configured to connect the corresponding row voltage and the corresponding column voltage to a ground or a known driven voltage in response to a pulse detection at the pixel.

Abstract: An imaging and pulse detection pixel and an array of imaging and pulse detection pixels are provided. Each imaging and pulse detection pixel includes an optical detection device connected directly to a first and second transistor only, a pulse detection circuit that operates on the signal read out from the optical detection device and outputs a pulse detection output signal suitable for detection of pulses, and an imaging circuit that operates on a signal read out from the optical detection device and outputs an image output signal suitable for generation of an image. A terminal of the optical detection device is directly connected to only a gate terminal of the first transistor and a non-gate terminal of the second transistor.

Abstract: A circuit having a buffered direct injection (BDI) module is provided for image lag mitigation. The BDI module includes an optical detector coupled to a buffer. The buffer has a pixel amplifier which includes no more than two transistors. The BDI module includes a first current mirror coupled to the BDI module. The first current mirror generates a modulating current based on the output of the optical detector. The BDI module further includes a second current mirror coupled to the first current mirror. The second current mirror is configured to generate either an amplified or attenuated photocurrent operable to optimize an imaging time and scene brightness of the optical detector. The BDI module further includes a reset circuit, coupled to the second current mirror, and being configured to reset an integration capacitor which integrates an image signal based on the output of the optical detector.

Abstract: An imager is provided that includes an integrated circuit. The integrated circuit includes at least one metal layer, a signal line extending in a first direction, and a pixel cell. The pixel cell includes imaging pixels and a metal interconnect. The imaging pixels include first, second, third, and fourth imaging pixels, arranged in two rows and two columns, each imaging pixel having a metal-insulator-metal (MiM) capacitor disposed on the at least one metal layer, the first and second imaging pixels being traversed by the signal line to receive signals from the signal line. The metal interconnect extends in a second direction different than the first direction and is coupled to the signal line and the third imaging pixel to transmit the signals to the third imaging pixel. The third imaging pixel is adjacent to the first imaging pixel and is disposed in a different column or row than the second imaging pixel.

Abstract: An imager is provided that includes an integrated circuit. The integrated circuit includes at least one metal layer, a signal line extending in a first direction, and a pixel cell. The pixel cell includes imaging pixels and a metal interconnect. The imaging pixels include first, second, third, and fourth imaging pixels, arranged in two rows and two columns, each imaging pixel having a metal-insulator-metal (MiM) capacitor disposed on the at least one metal layer, the first and second imaging pixels being traversed by the signal line to receive signals from the signal line. The metal interconnect extends in a second direction different than the first direction and is coupled to the signal line and the third imaging pixel to transmit the signals to the third imaging pixel. The third imaging pixel is adjacent to the first imaging pixel and is disposed in a different column or row than the second imaging pixel.

Abstract: A photosensitive pixel with gain stage is disclosed. The photosensitive pixel with gain stage may receive an input light stimulus and output a corresponding output voltage in response to the input light stimulus. The output voltage may correspond linearly to the magnitude of the input light stimulus over a linear operating region and logarithmically to the magnitude of the input light stimulus over a logarithmic operating region. In this manner, the photosensitive pixel with gain stage may be both sensitive to input light stimuli over the linear operating region and may exhibit dynamic range enabling non-saturated response to input light stimuli over the logarithmic operating region.

Abstract: A pixel master-slave photodiode bias control amplifier system is disclosed. The pixel master-slave photodiode bias control amplifier system may include a master pixel and one or more slave pixels. The slave pixel(s) may be connected to a portion of the master pixel. In this manner, components may be shared between/among the master pixel and the slave pixel(s); thus, for example, optimizing the component count of the pixel master-slave photodiode bias control amplifier system and the size occupied by the pixel master-slave photodiode bias control amplifier system.