Abstract: An imaging and pulse detection array includes: a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in the plurality of pixels and configured to detect a pulse on at least one of the pixels in the plurality of pixels, and each of the pixels in the plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein the imaging circuit and the pulse detection circuit include a shared portion.

Abstract: A circuit having a buffered direct injection (BDI) module is provided for image lag mitigation. The BDI module includes an optical detector coupled to a buffer. The buffer has a pixel amplifier which includes no more than two transistors. The BDI module includes a first current mirror coupled to the BDI module. The first current mirror generates a modulating current based on the output of the optical detector. The BDI module further includes a second current mirror coupled to the first current mirror. The second current mirror is configured to generate either an amplified or attenuated photocurrent operable to optimize an imaging time and scene brightness of the optical detector. The BDI module further includes a reset circuit, coupled to the second current mirror, and being configured to reset an integration capacitor which integrates an image signal based on the output of the optical detector.

Abstract: A pulse detecting imaging circuit includes a pixel array including multiple pixels arranged in at least one row and at least one column. The pixel array includes multiple row voltages and column voltages. Each of the row voltages is connected to each pixel in the corresponding row and each of the column voltages is connected to each pixel in the corresponding column. Each of said pixels includes an imaging circuit and a pulse detection circuit. An output of each pulse detection circuit is connected to a corresponding row voltage and a corresponding column voltage such that each pixel is configured to connect the corresponding row voltage and the corresponding column voltage to a ground or a known driven voltage in response to a pulse detection at the pixel.

Abstract: A device for capturing an image includes a first camera having a first lens optically coupled to a first image sensor of a first format. A second camera having a second lens is optically coupled to a second image sensor of a second format larger than the first format. A controller is operatively connected to the first and second cameras for selecting a sub-array of an optical image of the second image sensor to match an optical image captured by the first image sensor based on needed parallax correction between the first and second cameras.

Abstract: A pulse detector amplifier is disclosed. The pulse detector amplifier may have a detection switching leg that receives an input energy pulse. The pulse detector may have a mirror fast trigger including a trigger node and controlling a mirrored switching leg. The detection switching leg may trigger the trigger node in response to the input energy pulse. The pulse detector amplifier may also have a mirrored switching leg that controlled by the trigger node. The mirrored switching leg may control a voltage and/or current on the output node responsive to the input energy pulse. Thus, the pulse detector may generally include a cascode architecture, with a mirror fast trigger (which may include a FET) between the mirrored legs of the amplifier and enhancing the rapid triggering of the amplifier output. Thus the pulse detector may be power efficient, may have a small part count, and may be sensitive.

Abstract: A pixel cell includes a first integration capacitor, a second integration capacitor, a photo detector and a transistor. The first integration capacitor includes a first lead operatively coupled to the photo detector. The second integration capacitor includes a first lead. The transistor is operatively coupled between the leads of the first and second integration capacitors for enabling current flow between the photo detector and the second integration capacitor only once a threshold voltage is met on the first integration capacitor.