Abstract: Disclosed are biocompatible implants that combine a scaffold material for supporting long term repair of a soft tissue with an elongated member such as a suture for aiding in placement of the scaffold during a surgical procedure as well as for immediate mechanical reinforcement of a repair site. The components of an implant are combined such that a longitudinal load placed upon a composite structure can be borne primarily by the elongated member and the scaffold material is isolated from the longitudinal load. Thus, the scaffold material of a composite can be protected from damage due to applied loads and stresses during and following a surgical procedure.

Abstract: A financial securitization transaction, such as a collateralized debt obligation (CDO) transaction, that (i) is at least partially collateralized by a plurality of net lease assets where the tenants to the leases are financial institutions generally with assets of less than $10 billion, and (ii) where such securitization may not be fully collateralized by such net lease assets, in which case the remainder of the collateral for such securitization may consist predominantly of obligations (including trust preferred securities, debt and/or surplus notes) of financial institutions, and/or traunches of CDOs backed predominantly by such obligations. By restricting the assets to net lease assets in which the tenants are financial institutions and restricting the remaining assets to predominately obligations of financial institutions or tranches of CDOs backed by such obligations, more favorable ratings are obtainable from the ratings agencies for the securities backed by the net lease assets.

Abstract: An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths.

Abstract: Output buffer (100) translates input signals from one voltage range to a second voltage range. The second voltage range may be identical to the first range or may be greater. The particular range is programmable by one of several ways. This feature makes output buffer especially suitable for use in devices which must be compatible with two voltage ranges. Output buffer uses a bias generator (110) to limit the voltage across the gate oxide of its various transistors to a level which is consistent with the first voltage range.

Abstract: Level shifting circuit (36) utilizes self-timed pulse generators (40, 46) to provide a series of pulses in response to an input signal. The pulses are used to create a pulse of specified duration at a predetermined voltage level at first and second nodes (44, 45). In response to the predetermined pulses, shifted inverters (50, 52) provide a voltage output of either V.sub.DDH or V.sub.DDL, one of two different voltages which exist in a system utilizing the level shifter (36). In one form, level shifting circuit (36) may be used in an output buffer (60) to interface an integrated circuit designed to operate at a low supply voltage with additional integrated circuits operating at a higher supply voltage which could damage the gate oxide of the transistors in the low supply voltage integrated circuit.