Patents by Inventor Joydeep Guha

Joydeep Guha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10242883
    Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
  • Publication number: 20180374712
    Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
  • Patent number: 10134605
    Abstract: The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: November 20, 2018
    Assignee: Lam Research Corporation
    Inventor: Joydeep Guha
  • Publication number: 20180247798
    Abstract: A system for controlling processing state of a plasma process is provided. One example system includes a plasma reactor having a plurality of tuning knobs for making settings to operational conditions of the plasma reactor. A plurality of sensors of the plasma reactor is included, where each of the plurality of sensors is configured to produce a data stream of information during operation of the plasma reactor for carrying out the plasma process. A controller of the plasma reactor is configured to execute a multivariate processing that is configured to use as input desired processing state values that define intended measurable conditions within a processing environment of the plasma reactor and identify current plasma processing values. The multivariate processing uses a machine learning engine that receives as inputs the desired processing state values and data streams from the plurality of sensors during processing of the plasma process.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 30, 2018
    Inventors: Joydeep Guha, John Daugherty, Vahid Vahedi, Richard Alan Gottscho
  • Patent number: 9972478
    Abstract: Methods and systems for controlling processing state of a plasma reactor to initiate processing of production substrates and/or to determine a ready state of a reactor after the reactor has been cleaned and needs to be seasoned for subsequent production wafer processing are provided. The method initiate processing of a substrate in the plasma reactor using settings for tuning knobs of the plasma reactor that are approximated to achieve desired processing state values. A plurality of data streams are received from the plasma reactor during the processing of the substrate. The plurality of data streams are used to identify current processing state values. The method includes generating a compensation vector that identifies differences between the current processing state values and the desired processing state values. The generation of the compensation vector uses machine learning to improve and refile the identification and amount of compensation needed, as identified in the compensation vector.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 15, 2018
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, John Daugherty, Vahid Vahedi, Richard Alan Gottscho
  • Publication number: 20180082826
    Abstract: Methods and systems for controlling processing state of a plasma reactor to initiate processing of production substrates and/or to determine a ready state of a reactor after the reactor has been cleaned and needs to be seasoned for subsequent production wafer processing are provided. The method initiate processing of a substrate in the plasma reactor using settings for tuning knobs of the plasma reactor that are approximated to achieve desired processing state values. A plurality of data streams are received from the plasma reactor during the processing of the substrate. The plurality of data streams are used to identify current processing state values. The method includes generating a compensation vector that identifies differences between the current processing state values and the desired processing state values. The generation of the compensation vector uses machine learning to improve and refile the identification and amount of compensation needed, as identified in the compensation vector.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Joydeep Guha, John Daugherty, Vahid Vahedi, Richard Alan Gottscho
  • Patent number: 9899227
    Abstract: A system and method of ion milling performed in a plasma etch system including a plasma etch chamber, multiple process gas sources coupled to the plasma etch chamber, a radio frequency bias source and a controller. The plasma etch chamber including a substrate support. The substrate support being a non-pivoting and non-rotating substrate support. The substrate support capable of supporting a substrate to be processed on a top surface of the substrate support without use of a mechanical clamp device. The plasma etch chamber also including an upper electrode disposed opposite from the top surface of the substrate support. The radio frequency bias source is coupled to the substrate support. The controller is coupled to the plasma etch chamber, the multiple process gas sources and the radio frequency bias source. The controller including logic stored on computer readable media for performing an ion milling process in the plasma etch chamber.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: February 20, 2018
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Butsurin Jinnai, Jun Hee Han, Aaron Eppler
  • Publication number: 20180033657
    Abstract: A method for etching a substrate and removing byproducts includes a) setting process parameters of a processing chamber for a selective dry etch process; b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process; c) selectively etching a first film material of a substrate relative to a second film material of the substrate in the processing chamber during a first period; d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4; and e) purging the processing chamber at the second predetermined pressure for a second period.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 1, 2018
    Inventors: Pilyeon Park, Joydeep Guha
  • Patent number: 9870932
    Abstract: A method for etching a substrate and removing byproducts includes a) setting process parameters of a processing chamber for a selective dry etch process; b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process; c) selectively etching a first film material of a substrate relative to a second film material of the substrate in the processing chamber during a first period; d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4; and e) purging the processing chamber at the second predetermined pressure for a second period.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 16, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Pilyeon Park, Joydeep Guha
  • Patent number: 9837286
    Abstract: A method for selectively etching a tungsten layer on a substrate includes arranging a substrate including a tungsten layer on a substrate support. The substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper and lower chamber regions. The gas dispersion device includes a plurality of holes in fluid communication with the upper and lower chamber regions. The method further includes controlling pressure in the substrate processing chamber in a range from 0.4 Torr to 10 Torr; supplying an etch gas mixture including fluorine-based gas to the upper chamber region; striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil; and selectively etching the tungsten layer relative to at least one other film material of the substrate.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: December 5, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Dengliang Yang, Helen H. Zhu, George Matamis, Brad Jacobs, Joon Hong Park, Joydeep Guha
  • Publication number: 20170330728
    Abstract: A side tuning ring for a gas distribution device of a substrate processing system includes a first ring adjacent to a faceplate of the gas distribution device. The first ring surrounds the faceplate and defines a first plenum, communicates with a first gas source, and includes a first plurality of holes arranged to direct gas from the first gas source into a process chamber at a first angle. A second ring is adjacent to the first ring. The second ring surrounds the first ring and defines a second plenum, communicates with at least one of the first gas source and a second gas source, and includes a second plurality of holes arranged to direct gas from the at least one of the first gas source and the second gas source into the process chamber at the first angle or a second angle. The first ring and the second ring are detachable from the faceplate of the gas distribution device.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 16, 2017
    Inventors: Andrew Stratton Bravo, Joydeep Guha, Jatinder Kumar
  • Patent number: 9659783
    Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 23, 2017
    Assignee: Lam Research Corporation
    Inventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
  • Patent number: 9601319
    Abstract: A method for operating a substrate processing chamber includes after performing a process using a fluorine-based gas in the substrate processing chamber: a) during a first predetermined period, supplying a gas mixture to the substrate processing chamber including one or more gases selected from a group consisting of molecular oxygen, molecular nitrogen, nitric oxide and nitrous oxide and supplying RF power to strike plasma in the substrate processing chamber; b) during a second predetermined period after the first predetermined period, supplying molecular hydrogen gas and RF power to the substrate processing chamber; c) repeating a) and b) one or more times; d) purging the substrate processing chamber with molecular nitrogen gas; e) increasing chamber pressure; f) evacuating the substrate processing chamber; and g) repeating d), e) and f) one or more times.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: March 21, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Andrew Stratton Bravo, Joydeep Guha, Amit Pharkya
  • Publication number: 20170069511
    Abstract: A method for selectively etching a tungsten layer on a substrate includes arranging a substrate including a tungsten layer on a substrate support. The substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper and lower chamber regions. The gas dispersion device includes a plurality of holes in fluid communication with the upper and lower chamber regions. The method further includes controlling pressure in the substrate processing chamber in a range from 0.4 Torr to 10 Torr; supplying an etch gas mixture including fluorine-based gas to the upper chamber region; striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil; and selectively etching the tungsten layer relative to at least one other film material of the substrate.
    Type: Application
    Filed: February 3, 2016
    Publication date: March 9, 2017
    Inventors: Dengliang Yang, Helen H. Zhu, George Matamis, Brad Jacobs, Joon Hong Park, Joydeep Guha
  • Publication number: 20170040170
    Abstract: A processing volume is formed within an interior of a chamber between a top surface of a substrate support and a top dielectric window. An upper portion of the processing volume is a plasma generation volume. A lower portion of the processing volume is a reaction volume. A coil antennae is disposed above the dielectric window and connected to receive RF power. A process gas input is positioned to supply a process gas to the plasma generation volume. A series of magnets is disposed around a radial periphery of the chamber at a location below the top dielectric window. The series of magnets is configured to generate magnetic fields that extend across the processing volume. The series of magnets is positioned relative to the plasma generation volume such that at least a portion of the magnetic fields generated by the series of magnets is located below the plasma generation volume.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Inventors: Joydeep Guha, Aaron Eppler
  • Patent number: 9514955
    Abstract: A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: December 6, 2016
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Joydeep Guha, Camelia Rusu
  • Patent number: 9431269
    Abstract: The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: August 30, 2016
    Assignee: Lam Research Corporation
    Inventor: Joydeep Guha
  • Publication number: 20150364349
    Abstract: The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 17, 2015
    Inventor: Joydeep Guha
  • Publication number: 20150364337
    Abstract: A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material.
    Type: Application
    Filed: May 14, 2015
    Publication date: December 17, 2015
    Inventors: Joydeep Guha, Camelia Rusu
  • Publication number: 20150364339
    Abstract: The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber.
    Type: Application
    Filed: August 21, 2015
    Publication date: December 17, 2015
    Inventor: Joydeep Guha