Patents by Inventor Joydeep Ray

Joydeep Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180308195
    Abstract: One embodiment provides for a general-purpose graphics processing unit comprising multiple processing units and a pipeline manager to distribute a thread group to the multiple processing units, wherein the pipeline manager is to distribute the thread group as multiple thread sub-groups.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: BALAJI VEMBU, ALTUG KOKER, JOYDEEP RAY
  • Publication number: 20180307286
    Abstract: Methods and apparatus relating to techniques for dynamic control of liquid cooling pumps to provide thermal cooling uniformity are described. In an embodiment, modification is made to operation of one or more of: one or more cooling pumps or one or more fans, based at least in part on comparison of one or more detected temperature or noise values at one or more components of a processor with one or more corresponding threshold values. The processor may include the logic that causes the modification and one or more sensors, The sensors are thermally or acoustically coupled to the one or more components of the processor to determine the detected temperature or noise values. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Sanjeev S. Jahagirdar, Eric J. Asperheim, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, Prasoonkumar Surti, Kiran C. Veernapu
  • Publication number: 20180308202
    Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Liwei Ma, Elmoustapha Ould-Ahmed-Vall, Kamal Sinha, Joydeep Ray, Balaji Vembu, Sanjeev Jahagirdar, Vasanth Ranganathan, DUKHWAN Kim
  • Publication number: 20180307983
    Abstract: An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Narayan Srinivasa, Joydeep Ray, Nicolas C. Galoppo Von Borries, Ben Ashbaugh, Prasoonkumar Surti, Feng Chen, Barath Lakshmanan, Elmoustapha Ould-Ahmed-Vall, Liwei Ma, Linda L. Hurd, Abhishek R. Appu, John C. Weast, Sara S. Baghsorkhi, Justin E. Gottschlich, Chandrasekaran Sakthivel, Farshad Akhbari, Dukhwan Kim, Altug Koker, Nadathur Rajagopalan Satish
  • Publication number: 20180308197
    Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh, Subramaniam M. Maiyuran, Abhishek R. Appu, Joydeep Ray, Altug Koker, James A. Valerio, Eric J. Hoekstra, Arthur D. Hunter, JR.
  • Publication number: 20180307495
    Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.
    Type: Application
    Filed: November 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: ELMOUSTAPHA OULD-AHMED-VALL, BARATH LAKSHMANAN, TATIANA SHPEISMAN, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Anbang Yao, Ben J. Ashbaugh, Linda L. Hurd, Liwei Ma
  • Publication number: 20180308450
    Abstract: Methods and apparatus relating to techniques for provision of color mapping for better compression ratio are described. In an embodiment, a plurality of bits are moved from all channels of a first Red Green Blue Alpha (RGBA) space to an alpha channel of a second RGBA space. The plurality of the bits are selected from higher order bits of the first RGBA space. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Eric J. Hoekstra, Subramaniam Maiyuran, Prasoonkumar Surti, Eric G. Liskay, Joydeep Ray, Michael J. Norris, Wenyin Fu, Altug Koker
  • Publication number: 20180307985
    Abstract: A mechanism is described for facilitating barriers and synchronization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting thread groups relating to machine learning associated with one or more processing devices. The method may further include facilitating barrier synchronization of the thread groups across multiple dies such that each thread in a thread group is scheduled across a set of compute elements associated with the multiple dies, where each die represents a processing device of the one or more processing devices, the processing device including a graphics processor.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Sanjeev Jahagirdar, Vasanth Ranganathan
  • Publication number: 20180307306
    Abstract: Systems, apparatuses and methods may provide for technology to improve user experience when viewing simulated 3D objects on a display. Head and upper-body movements may be tracked and recognized as gestures to alter the displayed viewing angle. The technology provides for a very natural way to look around, under, or over objects.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Robert J. Johnston, Satyanarayana Avadhanam, Changliang Wang, Narayan Biswal, Archie Sharma, Richmond Hicks, Joydeep Ray, Abhishek R. Appu, Stanley J. Baran, Sang-Hee Lee, Atthar H. Mohammed, Jong Dae Oh, Hiu-Fai Chan, Sumit Mohan, Jill M. Boyce, Yi-Jen Chiu
  • Publication number: 20180307295
    Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Mohammed Tameem, Altug Koker, Kiran C. Veernapu, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Travis T. Schluessler, Jonathan Kennedy
  • Publication number: 20180307529
    Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Joydeep Ray, Balaji Vembu, James A. Valerio, Abhishek R. Appu
  • Publication number: 20180308203
    Abstract: A mechanism is described for facilitating sharing of data and compression expansion of models at autonomous machines. A method of embodiments, as described herein, includes detecting a first processor processing information relating to a neural network at a first computing device, where the first processor comprises a first graphics processor and the first computing device comprises a first autonomous machine. The method further includes facilitating the first processor to store one or more portions of the information in a library at a database, where the one or more portions are accessible to a second processor of a computing device.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Sara S. Baghsorkhi, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Joydeep Ray
  • Publication number: 20180310113
    Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Joydeep Ray, Travis T. Schluessler, Prasoonkumar Surti, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, James M. Holland, Jeffery S. Boles, Jonathan Kennedy, Louis Feng, Atsuo Kuwahara, Barnan Das, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Mayuresh M. Varerkar
  • Publication number: 20180308196
    Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Subramaniam M. Maiyuran, Eric J. Hoekstra, Prasoonkumar Surti, Balaji Vembu, Altug Koker
  • Publication number: 20180308277
    Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
  • Publication number: 20180308269
    Abstract: Systems, apparatuses and methods may a performance-enhanced computing system comprising a sensor for measuring luminance values corresponding to light focused onto the sensor at a plurality of pixel locations, a memory including a set of instructions, and a processor. The processor executes a set of instructions causing the system to generate a multi-segment tone mapping curve, generate a set of tone mapping values corresponding to the multi-segment tone mapping curve for equally spaced input values between zero and one for storage into a look up table, and process the luminance values using the look up table to apply the tone mapping curve to the luminance values of the pixels.
    Type: Application
    Filed: June 5, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Stanley J. Baran, Abhishek R. Appu, Sang-Hee Lee, Atthar H. Mohammed, Jong Dae Oh, Hiu-Fai R. Chan, Joydeep Ray, Kunjal Parikh, Changliang Wang, Srikanth Kambhatla, Gary Smith, Satyanarayana Avadhanam, Richmond Hicks, Robert J. Johnston, Narayan Biswal, Susanta Bhattacharjee
  • Publication number: 20180307533
    Abstract: A mechanism is described for facilitating multi-level scheduling of workloads in computing devices. A method of embodiments, as described herein, includes facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, where the workloads are associated with a device including a processor of a computing device.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Inventors: Kun Tian, David J. Cowperthwaite, Murali Ramadoss, Balaji Vembu, Zhi Wang, Eric C. Samson, Altug Koker, Abhishek R. Appu, Joydeep Ray
  • Publication number: 20180308280
    Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from pixel processing pipeline.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Subhajit Dasgupta, Srivallaba Mysore, Michael J. Norris, Vasanth Ranganathan, Joydeep Ray
  • Publication number: 20180307633
    Abstract: An apparatus to facilitate source synchronous signaling is disclosed. The apparatus includes transfer protocol logic to provide for source synchronous transfer of data within an interconnect fabric, including one or more synchronizers having logic to a transmit data signal and a source clock (clk) signal during the transfer of data.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Joydeep Ray, Vasanth Ranganathan, Abhishek R. Appu
  • Publication number: 20180307984
    Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Abhishek R. Appu, Kamal Sinha, Joydeep Ray, Balaji Vembu, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, John C. Weast, Justin E. Gottschlich, Prasoonkumar Surti, Chandrasekaran Sakthivel, Farshad Akhbari, Nadathur Rajagopalan Satish, Liwei Ma, Jeremy Bottleson, Eriko Nurvitadhi, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy, Vasanth Ranganathan, Sanjeev Jahagirdar