Patents by Inventor Joydeep Ray

Joydeep Ray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180308212
    Abstract: A mechanism is described for facilitating selective skipping of compression cycles in computing devices. A method of embodiments, as described herein, includes facilitating determining a first current output relating to compression of a current set of data to be same as a previous output from compression of a previous set of data, and turning off a compression engine to skip compression of the current set of data.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Kiran C. Veernapu, Abhishek R. Appu, Prasoonkumar Surti, Arijit Mukhopadhyay, Altug Koker, Joydeep Ray
  • Publication number: 20180308208
    Abstract: An apparatus to facilitate compute optimization is disclosed.
    Type: Application
    Filed: November 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Publication number: 20180308206
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.
    Type: Application
    Filed: September 7, 2017
    Publication date: October 25, 2018
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Publication number: 20180308214
    Abstract: An apparatus to facilitate data scrambling is disclosed. The apparatus includes a memory and a processing unit including a processing core to generate a memory write operation to write data to the memory and logic to scramble the write data to generate scrambled data.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Abhishek R. Appu, Vasanth Ranganathan
  • Publication number: 20180307613
    Abstract: A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu
  • Publication number: 20180308209
    Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Murali Ramadoss, Balaji Vembu, Eric C. Samson, Kun Tian, David J. Cowperthwaite, Altug Koker, Zhi Wang, Joydeep Ray, Subramaniam M. Maiyuran, Abhishek R. Appu
  • Publication number: 20180307899
    Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corproation
    Inventors: Barnan Das, MAYURESH M. VARERKAR, NARAYAN BISWAL, STANLEY J. BARAN, GOKCEN CILINGIR, NILESH V. SHAH, ARCHIE SHARMA, SHERINE ABDELHAK, Praneetha Kotha, Neelay Pandit, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Abhishek R. Appu, Altug Koker, Joydeep Ray
  • Publication number: 20180307485
    Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Ramkumar Ravikumar, Kiran C. Veernapu, Prasoonkumar Surti, Vasanth Ranganathan
  • Publication number: 20180308200
    Abstract: An apparatus to facilitate compute optimization is disclosed.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • Publication number: 20180307971
    Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corpoartion
    Inventors: Kamal Sinha, Balaji Vembu, Eriko Nurvitadhi, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Farshad Akhbari, Narayan Srinivasa, Feng Chen, Dukhwan Kim, Nadathur Rajagopalan Satish, John C. Weast, Mike B. MacPherson, Linda L. Hurd, Vasanth Ranganathan, Sanjeev S. Jahagirdar
  • Publication number: 20180308213
    Abstract: A mechanism is described for facilitating fabric-based compression and/or decompression of data at computing devices. A method of embodiments, as described herein, includes compressing contents of a data stream traveling through an internal fabric between a source component and a destination component, wherein the contents are compressed on the internal fabric.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu
  • Publication number: 20180308207
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.
    Type: Application
    Filed: October 31, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Publication number: 20180308201
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Publication number: 20180308266
    Abstract: Methods and apparatus relating to techniques for provision of low power foveated rendering to save power on GPU (Graphics Processing Unit) and/or display are described. In various embodiment, brightness/contrast, color intensity, and/or compression ratio applied to pixels in a fovea region are different than those applied in regions surrounding the fovea region. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Wenyin Fu, Nikos Kaburlasos, Jacek Kwiatkowski, Travis T. Schluessler, John H. Feit, Joydeep Ray
  • Publication number: 20180307606
    Abstract: A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, James A. Valerio, Prasoonkumar Surti
  • Publication number: 20180309969
    Abstract: Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Karthik Vaidyanathan, Prasoonkumar Surti, Michael Apodaca, Murali Ramadoss, Abhishek Venkatesh
  • Publication number: 20180308256
    Abstract: An apparatus to facilitate compute compression is disclosed. The apparatus includes a graphics processing unit including mapping logic to map a first block of integer pixel data to a compression block and compression logic to compress the compression block.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Nadathur Rajagopalan Satish, Narayan Srinivasa, Feng Chen, Dukhwan Kim, Farshad Akhbari
  • Publication number: 20180308267
    Abstract: Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventor: Joydeep Ray
  • Patent number: 10109039
    Abstract: Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Prasoonkumar Surti
  • Patent number: 10108850
    Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Barnan Das, Mayuresh M. Varerkar, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Sherine Abdelhak, Praneetha Kotha, Neelay Pandit, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Abhishek R. Appu, Altug Koker, Joydeep Ray