Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

Abstract: An apparatus to facilitate cache replacement is disclosed. The apparatus includes a cache memory and cache replacement logic to manage data in the cache memory. The cache replacement logic includes tracking logic to track addresses accessed at the cache memory and replacement control logic to monitor the tracking logic and apply a replacement policy based on information received from the tracking logic.

Abstract: Systems, apparatuses, and methods may provide for technology to process multi-resolution images by identifying pixels at a boundary between pixels of different resolutions, and selectively smoothing the identified pixels.

Abstract: A shared local memory data crossbar may be implemented in multiple stages. With this approach, the number of multiplexer cells can be reduced by fifty percent (50%) or more in some embodiments.

Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.

Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

Abstract: One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single instruction multiple data (SIMD) message from the first execution unit; second logic coupled with a second execution unit, the second logic to receive a second SIMD message from the second execution unit; and third logic coupled with a bank of shared local memory (SLM), the third logic to receive a first request to access the bank of SLM from the first logic, a second request to access the bank of SLM from the second logic, and in a single access cycle, schedule a read access to a read port for the first request and a write access to a write port for the second request.

Abstract: The invention relates to a composition for coating a frozen confection, the composition comprising, expressed in weight % based on the total weight of the coating, 30 to 80 wt % of fat, which comprises a fat blend of hard fat and liquid oil, and 20 to 70 wt % of non-fat solids, wherein, the coating composition comprises, less than 25 wt % of saturated fatty acid, 10-60 wt %, preferably 20-40% of monounsaturated fatty acid and less than 10%, preferably less than 5% of polyunsaturated fatty acid, and wherein, the saturated fatty acid comprises between 12-24C-atoms and the unsaturated fatty acid contains 18C-atoms or more than 18C-atoms. The invention also relates to a process of making this composition and a frozen confection at least partly coated with the composition.

Abstract: The invention relates to a method of manufacturing a frozen confection comprising providing a frozen confection to be coated, providing a liquid coating composition which comprises less than 25% of saturated fatty acids and which solidifies in a two-step crystallization at a temperature of ?15° C., at least partly coating the frozen confection, letting the coating composition perform a first crystallization event, and letting the at least partly coated frozen confection perform a second crystallization event. The invention also relates to a at least partly coated frozen confection obtained by this method of manufacturing.

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a compute cluster including multiple compute units, a stall notification module to detect that one or more compute units in the compute cluster are stalled and send stall notification, and a rebalance module to receive the stall notification, the rebalance module to migrate a first workload from one or more stalled compute units in response to the stall notification.

Abstract: Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.

Abstract: An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

Abstract: A graphics processor may be assigned a number of banks in a shared local memory to reduce the number of bank conflicts. In some cases, the number of banks may be higher than the single instruction multiple data slot number times the number of messages per cycle. The actual number of banks may be set to the next higher relatively prime number of 2n and 3 where n is 0-5.

Abstract: One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single instruction multiple data (SIMD) message from the first execution unit; second logic coupled with a second execution unit, the second logic to receive a second SIMD message from the second execution unit; and third logic coupled with a bank of shared local memory (SLM), the third logic to receive a first request to access the bank of SLM from the first logic, a second request to access the bank of SLM from the second logic, and in a single access cycle, schedule a read access to a read port for the first request and a write access to a write port for the second request.

Abstract: Methods and apparatus relating to buffering graphics tiled resource translations in a data port controller TLB (Translation Lookaside Buffer) are described. In an embodiment, controller logic causes storage of information corresponding to a tiled resource in a first entry of a Translation Lookaside Buffer (TLB) in response to a request corresponding to the tiled resource. A second entry of the TLB is capable of storing data corresponding to a coherent memory request. The tiled resource comprise data corresponding to a portion of an image. Other embodiments are also disclosed and claimed.

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a general-purpose hashing function block that defines a default interleaving sequence for memory requests to alternately access the multiple memory channels and multiple specific-purpose hashing function blocks that define different interleaving sequences for the memory requests to alternately access the multiple memory channels. The MCU also includes a hashing-function selection block. The hashing-function selection block is operable to select one of the specific-purpose hashing function blocks or the general-purpose hashing function block for a current memory request in view of a requesting functional unit originating the current memory request.

Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.