Abstract: Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Abstract: A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a general-purpose hashing function block that defines a default interleaving sequence for memory requests to alternately access the multiple memory channels and multiple specific-purpose hashing function blocks that define different interleaving sequences for the memory requests to alternately access the multiple memory channels. The MCU also includes a hashing-function selection block. The hashing-function selection block is operable to select one of the specific-purpose hashing function blocks or the general-purpose hashing function block for a current memory request in view of a requesting functional unit originating the current memory request.

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

Abstract: Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.

Abstract: Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.

Abstract: An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.

Abstract: Systems and methods for write allocation by a two-level memory controller. An example processing system comprises: a processing core; a memory controller communicatively coupled to the processing core; and a system memory communicatively coupled to the memory controller, the system memory comprising a first level memory and a second level memory; wherein the memory controller is configured, responsive to determining that a memory block referenced by a memory write request is not present in the first level memory, to allocate a new first level memory block without retrieving the memory block referenced by the request from the second level memory, wherein the memory write request is represented by an overwrite type memory write request.

Abstract: Technologies for one-level memory (1LM) and two-level memory (2LM) configurations in a common platform are described. A processor includes a first memory interface coupled to a first memory device that is located off-package of the processor and a second memory interface coupled to a second memory device that is located off-package of the processor. The processor also includes a multi-level memory controller (MLMC) coupled to the first memory interface and the second memory interface. The MLMC includes a first configuration and a second configuration. The first memory device is a random access memory (RAM) of a one-level memory (1LM) architecture in the first configuration. The first memory device is a first-level RAM of a two-level memory (2LM) architecture in the second configuration and the second memory device is a second-level non-volatile memory (NVM) of the 2LM architecture in the second configuration.

Abstract: A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

Abstract: Multi-level memory architecture technologies are described. One processor includes a requesting unit, a first memory interface to couple to a far memory (FM), a second memory interface to couple to a near memory (NM) and a multi-level memory controller (MLMC) coupled to the requesting unit, the first memory interface and the second memory interface. The MLMC is to write data into a memory page of NM in response to a request from the requesting unit to retrieve the memory page from FM. The MLMC receives a hint from the requesting unit and clears a writeback bit for the memory page indicated in the hint. The hint indicates that the data contained in the memory page of the NM is not to be subsequently requested by the requesting unit. The MLMC starts a writeback operation of a memory sector including the memory page and one or more additional memory pages.

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Abstract: Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.

Abstract: According to one embodiment of the invention, an integrated circuit device comprises an interconnect, at least one compute engine and a control unit. Coupled to the at least one compute engine via the interconnect, the control unit to analyze heuristic information from the at least one compute engine and to increase or decrease a bandwidth of the interconnect based on the heuristic information.