Patents by Inventor Joyeeta Nag

Joyeeta Nag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11348832
    Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 31, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
  • Publication number: 20220165937
    Abstract: A method of forming a magnetoresistive random access memory (MRAM) device includes providing a first die containing a selector material layer located over a first substrate, providing a second die containing a MRAM layer stack located over a second substrate, and bonding the first die to the second die.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: Jeffrey LILLE, Joyeeta NAG, Raghuveer S. MAKALA
  • Publication number: 20220157966
    Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Bhagwati PRASAD, Joyeeta NAG, Seung-Yeul YANG, Adarsh RAJASHEKHAR, Raghuveer S. MAKALA
  • Publication number: 20220157852
    Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Bhagwati PRASAD, Joyeeta NAG, Seung-Yeul YANG, Adarsh RAJASHEKHAR, Raghuveer S. MAKALA
  • Publication number: 20210407943
    Abstract: A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 30, 2021
    Inventors: Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Joyeeta NAG
  • Patent number: 11031435
    Abstract: A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 8, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Michael Grobis, Joyeeta Nag, Derek Stewart
  • Publication number: 20200395410
    Abstract: A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: Michael GROBIS, Joyeeta NAG, Derek STEWART
  • Patent number: 10727122
    Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
  • Publication number: 20190326170
    Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Benjamin C. BACKES, Brian A. COHEN, Joyeeta NAG, Carl J. RADENS
  • Patent number: 10395984
    Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin C. Backes, Brian A. Cohen, Joyeeta Nag, Carl J. Radens
  • Patent number: 9793216
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Patent number: 9784917
    Abstract: Embodiments are directed to a coupler system having an interposer configured to couple optical signals. The interposer includes at least one optoelectronic component formed on a glass substrate. The interposer further includes at least one waveguide formed on the glass substrate and configured to couple the optical signals to or from the at least one optoelectronic component, wherein the at least one waveguide comprises a waveguide material having grain diameters greater than about one micron and an optical loss less than about one decibel per centimeter of optical propagation.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Joyeeta Nag, Jason S. Orcutt, Jean-Olivier Plouchart, Spyridon Skordas
  • Patent number: 9748235
    Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Aritra Dasgupta, Benjamin G. Moser, Mohammad Hasanuzzaman, Murshed M. Chowdhury, Shahrukh A. Khan, Shafaat Ahmed, Joyeeta Nag
  • Publication number: 20170236780
    Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.
    Type: Application
    Filed: April 12, 2017
    Publication date: August 17, 2017
    Inventors: Joyeeta Nag, Shishir K. Ray, Andrew H. Simon, Oleg Gluschenkov, Siddarth A. Krishnan, Michael P. Chudzik
  • Publication number: 20170221889
    Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 3, 2017
    Inventors: Aritra Dasgupta, Benjamin G. Moser, Mohammad Hasanuzzaman, Murshed M. Chowdhury, Shahrukh A. Khan, Shafaat Ahmed, Joyeeta Nag
  • Publication number: 20170213792
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 27, 2017
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Patent number: 9679810
    Abstract: An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Shishir K. Ray, Andrew H. Simon, Oleg Gluschenkov, Siddarth A. Krishnan, Michael P. Chudzik
  • Patent number: 9620396
    Abstract: Disclosed is a process of annealing through silicon vias (TSVs) or other deeply buried metallic interconnects using a back side laser annealing process. The process provides several advantages including sufficient grain growth and strain relief of the metal such that subsequent thermal processes do not cause further grain growth; shorter anneal times thereby reducing cycle time of 3D device fabrication; and reduced pattern sensitivity of laser absorption.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Andrew J. Martin, Joyeeta Nag
  • Publication number: 20170097467
    Abstract: Embodiments are directed to a coupler system having an interposer configured to couple optical signals. The interposer includes at least one optoelectronic component formed on a glass substrate. The interposer further includes at least one waveguide formed on the glass substrate and configured to couple the optical signals to or from the at least one optoelectronic component, wherein the at least one waveguide comprises a waveguide material having grain diameters greater than about one micron and an optical loss less than about one decibel per centimeter of optical propagation.
    Type: Application
    Filed: October 5, 2015
    Publication date: April 6, 2017
    Inventors: Stephen M. Gates, Joyeeta Nag, Jason S. Orcutt, Jean-Olivier Plouchart, Spyridon Skordas
  • Patent number: 9502325
    Abstract: A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This continuous cooling channel may provide a path for a cooling source such as a fluid pumped from an external fluidic-cooling circulation driver to make physical contact locally with and cool the back end levels within the IC chip that may generate heat as a byproduct of the IC device's routine operations. Such a cooling structure is achieved by removing a horizontal portion of a barrier layer from an intermediate region of an interlevel interconnect structure, selective to a vertical portion of the barrier layer located on a sidewall of the interlevel interconnect structure, using gas cluster ion beam etching as well as removing the bulk conductor by additional means.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Vincent J. McGahay, Joyeeta Nag, Yiheng Xu