Abstract: A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a metal gate structure formed over a fin structure of the substrate. The semiconductor structure further includes a spacer formed on a sidewall of the metal gate structure and a source/drain structure formed in the fin structure. In addition, the spacer is in direct contact with the fin structure.

Abstract: A semiconductor device with effective FinFET isolation and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and first dielectric features over the substrate and separating the dummy gate stacks. The method further includes removing the dummy gate stacks thereby forming a first trench and a second trench that expose first and second portions of the active fin respectively. The method further includes removing the first portion of the active fin and forming a gate stack in the second trench, the gate stack engaging the second portion of the active fin. The method further includes filling the first trench with a second dielectric material that effectively isolates the second portion of the active fin.

Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.

Abstract: A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

Abstract: Present disclosure provides a semiconductor structure, including a substrate having a center portion and an edge portion, an isolation layer over the substrate; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer, a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate, and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate. A lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.

Abstract: A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.

Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a first gate stack and a second gate stack over different portions of a fin feature formed on a substrate, forming a first dielectric layer in a space between the first and second gat stacks, removing the first gate stack to form a first gate trench, therefore the first gate trench exposes a portion of the fin feature. The method also includes removing the exposed portion of the fin feature and forming an isolation feature in the first gate trench.

Abstract: A method includes providing a first mask pattern over a substrate, forming first spacers adjoining sidewalls of the first mask pattern, removing the first mask pattern, forming second spacers adjoining sidewalls of the first spacers, forming a filling layer over the substrate and between the second spacers, and forming a second mask pattern over the substrate.

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

Abstract: In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues.

Abstract: In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.

Abstract: The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.

Abstract: A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET.

Abstract: A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues.

Abstract: A structure includes a substrate, a gate structure over the substrate, a dielectric layer over the substrate, and a cap over a gate electrode of the gate structure. Top surfaces of the dielectric layer and gate electrode are co-planar. The gate structure extends a gate lateral distance between first and second gate structure sidewalls. The cap extends between first and second cap sidewalls. A first cap portion extends from a midline of the gate structure laterally towards the first gate structure sidewall and to the first cap sidewall a first cap lateral distance, and a second cap portion extends from the midline laterally towards the second gate structure sidewall and to the second cap sidewall a second cap lateral distance. The first cap lateral distance and the second cap lateral distance are at least half of the gate lateral distance.

Abstract: One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. In some embodiments, a semiconductor structure includes a substrate, a first lightly doped drain (LDD), a second LDD, an interface layer (IL), a high-k stack, a gate region, a dummy poly region, a first hard mask (HM) region, a second HM region, and a seal spacer region. The HK stack has a HK stack width and the gate region has a gate region width that is less than or substantially equal to the HK stack width. Because of the increased width of the HK stack, some of the HK stack likely overlaps some of the first LDD or the second LDD. In this manner, a saturation current and a threshold voltage associated with the semiconductor structure are improved. The increased width of the HK stack also protects more of the IL during LDD implanting.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.