Abstract: A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity.

Abstract: In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

Abstract: In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.

Abstract: A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

Abstract: In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.

Abstract: A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET.

Abstract: A semiconductor device includes a substrate having first and second fins extending lengthwise generally along a same line; a first gate stack over the substrate and engaging the first fin; a second gate stack over the substrate and engaging the second fin; a first isolation structure disposed between the first and second fins; and spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the first isolation structure.

Abstract: A method for forming a fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract: A fin-like field-effect transistor (Fin-FET) device includes a substrate, a fin structure disposed on the substrate, and an isolation structure disposed adjacent to the fin structure. The fin structure includes a recessed structure, which a bottom of the recessed structure is below a top surface of the isolation structure.

Abstract: A semiconductor device includes a semiconductor substrate; an isolation region over the semiconductor substrate; and two fin features over the semiconductor substrate and protruding above the isolation region. The two fin features are generally aligned along their longitudinal direction. The device further includes two gate structures disposed over a top surface of the isolation region and engaging top surface and sidewalls of the two fin features respectively. The device further includes source and drain features disposed over the fin features and on both sides of each of the gate structures. The device further includes a first structure disposed between and protruding above the fin features, wherein a bottom surface of the first structure is below the top surface of the isolation region.

Abstract: Present disclosure provides a semiconductor structure, including a substrate having a center portion and an edge portion, an isolation layer over the substrate; a semiconductor fin with a top surface and a sidewall surface, partially positioning in the isolation layer, a first gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at an edge portion of the substrate, and a second gate covering a portion of the top surface and a portion of the sidewall surface of the semiconductor fin, positioning at a center portion of the substrate. A lower width of the first gate in proximity to the isolation layer is smaller than an upper width of the first gate in proximity to top surface of the semiconductor fin.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a substrate and a first fin structure and a second fin structure extending above the substrate. The FinFET device structure also includes a first transistor formed on the first fin structure and a second transistor formed on the second fin structure. The FinFET device structure further includes an inter-layer dielectric (ILD) structure formed in an end-to-end gap between the first transistor and the second transistor, and the end-to-end gap has a width in a range from about 20 nm to about 40 nm.

Abstract: A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET.

Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming first and second gate stacks over first and second portions of a fin feature respectively; filling a space between the first and second gate stacks with a dielectric layer; removing the first and second gate stacks to form first and second trenches respectively; and removing the first portion of the fin feature through the first trench while keeping the second portion of the fin feature in the second trench. The method further includes, after the removing of the first portion, depositing a gate dielectric layer and a gate electrode layer in the first and second trenches.

Abstract: A semiconductor device with effective FinFET isolation and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and first dielectric features over the substrate and separating the dummy gate stacks. The method further includes removing the dummy gate stacks thereby forming a first trench and a second trench that expose first and second portions of the active fin respectively. The method further includes removing the first portion of the active fin and forming a gate stack in the second trench, the gate stack engaging the second portion of the active fin. The method further includes filling the first trench with a second dielectric material that effectively isolates the second portion of the active fin.

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat area, and the flat area extends in the second direction and the third direction.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.

Abstract: A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues.