Abstract: The present disclosure relates to a cathode active material for an all-solid-state battery with a controlled particle size and a method for preparing the same. In particular, the cathode active material includes lithium and a transition metal, wherein the cathode active material has a single peak in the range of 1 ?m to 10 ?m as a result of particle size distribution (PSD) analysis.

Abstract: A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active pattern and the first insulating interlayer, a buffer layer covering the second gate structure on the first active pattern and the first insulating interlayer, a second insulating interlayer formed on the buffer layer, and a contact plug formed through the first and second insulating interlayers, which contacts with the substrate and is insulated from the second gate structure by the buffer layer. Operation failures of a transistor in the stacked semiconductor device can be reduced because the buffer layer prevents a word line from being electrically connected to the contact plug.

Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

Abstract: In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Abstract: A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active pattern and the first insulating interlayer, a buffer layer covering the second gate structure on the first active pattern and the first insulating interlayer, a second insulating interlayer formed on the buffer layer, and a contact plug formed through the first and second insulating interlayers, which contacts with the substrate and is insulated from the second gate structure by the buffer layer. Operation failures of a transistor in the stacked semiconductor device can be reduced because the buffer layer prevents a word line from being electrically connected to the contact plug.

Abstract: In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having a width which is wider than that of the structures are formed on the structures. A second insulation film is formed to cover the resultant structures without voids between the structures.

Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.

Abstract: In a method of manufacturing a phase-changeable memory device, a lower electrode is formed on a substrate. Silicon oxynitride is then deposited on the lower electrode at a temperature of about 450° C. to about 650° C. to form an insulating interlayer that is relatively dense on the lower electrode. The insulating interlayer is partially etched to form a contact hole exposing the lower electrode. A phase-changeable material layer pattern filling up the contact hole is formed on the insulating interlayer such that the phase-changeable material layer pattern makes contact with the lower electrode.

Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.

Abstract: In a layer structure, a method of forming the layer structure, a method of manufacturing a capacitor having the layer structure and a method of manufacturing a semiconductor device having the capacitor, a structure may be formed on a substrate. A first insulation layer including at least one kind of impurities may be formed on the structure. A flatness of the first insulation layer may fluctuate according to the type and concentration of the impurities. The first insulation layer may include silicate glass doped with first impurities including an element in Group III and/or second impurities including an element in Group V. The flatness of the first insulation layer may improve in proportion to the concentration of the first impurities whereas in inverse proportion to the concentration of the second impurities. Accordingly, the flatness of the first insulation layer may be determined by adjusting the type and concentration of the impurities.

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

Abstract: In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having a width which is wider than that of the structures are formed on the structures. A second insulation film is formed to cover the resultant structures without voids between the structures.

Abstract: In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having a width which is wider than that of the structures are formed on the structures. A second insulation film is formed to cover the resultant structures without voids between the structures.

Abstract: Methods of forming trench isolations are provided. A method includes providing a semiconductor substrate having a cell array region and a peripheral region. At least one cell trench in the cell array region and at least one peripheral trench wider than the cell trench in the peripheral region of the substrate are formed. The cell and the peripheral trenches have sidewalls. A first dielectric layer that partially fills the cell and peripheral trenches is formed over the substrate. At least one photoresist pattern that exposes at least the cell trench partially filled with the first dielectric layer is formed over the substrate. The first dielectric layer formed on the sidewalls of the exposed cell trench is etched by using the photoresist pattern as a etch mask. Subsequently, the photoresist pattern is removed. A second dielectric layer filling the cell and peripheral trenches is formed over the substrate where the photoresist pattern is removed.

Abstract: In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.

Abstract: A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.

Abstract: Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate, and the dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate. A first metal layer is formed in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate. After preferentially forming the first metal layer in the contact hole, a second metal layer is formed on the surface of the interlevel dielectric film opposite the integrated circuit substrate.