Abstract: A user equipment (UE) and a method performed by the UE are provided. The method includes transitioning from a radio resource control (RRC) inactive (RRC_INACTIVE) state to an RRC idle (RRC_IDLE) state upon determining that the UE has failed to find a suitable cell and camped on an acceptable cell; and discarding a radio access network (RAN) notification area (RNA) configuration that comprises at least one of a list of tracking area identities (IDs) or a list of RAN area IDs in response to the transitioning from the RRC_INACTIVE state to the RRC_IDLE state. The acceptable cell fulfills a minimum set of requirements to initiate an emergency call and to receive one or more Earthquake & Tsunami Warning System (ETWS) and Commercial Mobile Alert System (CMAS) notifications. The suitable cell provides normal services. The acceptable cell provides limited services.

Abstract: A liquid level controlling apparatus includes a plurality of main sinks, a storage sink, a pump and a connection tube. One of the plurality of main sinks includes a transmission port and a first liquid level detector. The storage sink includes a delivery port and a second liquid level detector. The pump includes an outlet and an inlet. The connection tube includes an rehydration tube and an drain tube. The rehydration tube has a first rehydration section and a second rehydration section. The first rehydration section is connected between the delivery port and the inlet. The second rehydration section is connected between the outlet and the transmission port. The drain tube has a first drain section and a second drain section. The first drain section is connected between the transmission port and the inlet. The second drain section is connected between the outlet and the delivery port.

Abstract: A method for LBT failure detection performed by a UE is provided. The method includes: receiving, by a MAC entity of the UE, an LBT failure indication from a lower layer for all UL transmissions; increasing an LBT failure counter when the MAC entity receives the LBT failure indication; determining an LBT failure event occurs when the LBT failure counter is greater than or equal to a threshold; and resetting the LBT failure counter after the MAC entity has not received the LBT failure indication for a time period.

Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.

Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.

Abstract: An antenna structure includes a first substrate and a second substrate. The first substrate includes: a semiconductor chip configured to transmit or receive a first radio-frequency (RF) signal; a first ground layer configured to provide ground to the semiconductor chip; and a signal layer arranged on a side of the first substrate opposite to the semiconductor chip and configured to transmit the first RF signal. The second substrate has an antenna array formed of antenna cells, each of the antenna cells including: a first antenna layer configured to radiate second RF signals based on the first RF signal; a second ground layer configured to provide ground to the first antenna layer. The antenna device further includes a plurality of connectors electrically coupling the semiconductor chip to the antenna array.

Abstract: A liquid level controlling system includes a main sink, a storage sink and a connection tube. The main sink includes a transmission port and a first liquid level detector. The transmission port is formed on a bottom of the main sink. The first liquid level detector is disposed on a top of the main sink. The storage sink includes a liquid outlet, a liquid inlet and a second liquid level detector. The connection tube is disposed between the main sink and the storage sink. The connection tube includes an rehydration tube and an drain tube. Two ends of the rehydration tube are respectively connected to the transmission port and the liquid outlet. Two ends of the drain tube are respectively connected to the transmission port and the liquid inlet.

Abstract: A gaming system and an operation method of a gaming server thereof are provided. The gaming system includes multiple player devices and the gaming server. The gaming server establishes a network connection with the player devices. In response to one of the player devices initiating a game, the gaming server sends a game notification to the player devices according to a player list. The gaming server determines a common throughput between the player devices based on a response of each of the player devices to the game notification.

Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Abstract: A method for a user equipment (UE) for cell selection while the UE is in a radio resource control (RRC) Inactive state is provided. The method receives, via control signaling, a configuration indicating a target frequency carrier and a corresponding target core network (CN) type. The method then causes the UE to transition from an RRC Connected state to the RRC Inactive state based on the received configuration. While the UE is in the RRC Inactive state, the method selects a suitable cell among a plurality of suitable cells that are associated with the target frequency carrier. The method selects the suitable cell irrespective of the received target CN type.

Abstract: Embodiments of this application disclose a full-duplex self-interference cancellation method and apparatus. The full-duplex self-interference cancellation method may be applied to the field of radio frequency self-interference cancellation in a full-duplex scenario. The full-duplex self-interference cancellation method is implemented by a full-duplex self-interference cancellation apparatus with self-interference reconstruction modules of two levels, and the full-duplex self-interference cancellation apparatus is implemented by a terminal. This greatly reduces hardware implementation complexity and costs of the second self-interference reconstruction module, and improves a full-duplex self-interference cancellation capability.

Abstract: A keyboard includes a base plate, a plurality of keys and a backlight module. The base plate has a short-axis direction and a long-axis direction. The keys are disposed on the base plate. The backlight module is disposed on the base plate and includes a shielding sheet, a light guide plate and a reflecting sheet. The light guide plate is disposed on a lower surface of the shielding sheet. The light guide plate includes a plurality of light guide structures corresponding to the keys respectively. Each of the light guide structures includes a ring portion and at least one bend line portion. The bend line portion connects to the ring portion, and the ring portion is formed by a plurality of bending portions. The reflecting sheet is disposed below the light guide plate.

Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.

Abstract: A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate and a dielectric layer on the substrate; forming a hole in the dielectric layer; forming an initial barrier material layer and a conductive layer on an upper surface of the dielectric layer and in the hole; removing part of the initial barrier material layer and part of the conductive layer to form a barrier material layer and a via element in the hole respectively and expose the upper surface of the dielectric layer. An upper surface of the barrier material layer is higher than the upper surface of the dielectric layer.

Abstract: In various embodiments, a washable mat system comprises a top cover removably attached to a bottom pad. The top cover comprises layers of material, including a top layer with a tufted loop pile, a water-resistant internal layer, and a bottom knit surface. The top cover is sufficiently malleable to be folded, rolled, compressed, and withstand multiple wash and dry cycles while maintaining material stability. The bottom pad also comprises layers of material, including a top layer to removably attach to the bottom knit surface of the top cover, an internal cushioning layer, and a non-slip bottom surface.

Abstract: An electronic device including a substrate, a first electrode layer, a photodiode, an insulating layer, a second electrode layer, and a first transparent conductive layer is provided. The first electrode layer is disposed on the substrate. The photodiode is disposed on the first electrode layer and is electrically connected to the first electrode layer. The insulating layer is disposed on the photodiode. The second electrode layer is disposed on the insulating layer and is electrically connected to the photodiode. The first transparent conductive layer is disposed on the insulating layer and contacts the second electrode layer. A manufacturing method of an electronic device is also provided.

Abstract: A method performed by a BS for CHO is provided. The method includes transmitting a CHO command to a UE, the CHO command including a CHO command ID and a measurement ID associated with the CHO command ID; causing the UE to execute the CHO command to handover to a target BS when a trigger condition associated with the measurement ID is fulfilled; causing the UE to forgo transmitting the measurement report during the execution of the CHO command despite the UE being configured, via a report configuration associated with the measurement ID, to transmit the measurement report; transmitting, to the UE, a message that causes the UE to remove the CHO command; and after transmitting the message to the UE, determining that the report configuration is removed by the UE without transmitting, to the UE, an instruction to remove the report configuration.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.