Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a fin element, forming an isolation structure to surround the fin element, forming a dummy gate dielectric layer across the fin structure over the isolation structure, forming a dummy gate electrode layer on the dummy gate dielectric layer, partially etching the dummy gate electrode layer and the dummy gate dielectric layer to form a trench, removing the first semiconductor layers to form gaps, forming a gate stack on the remaining portion of the dummy gate electrode layer and filling the trench and the gaps.

Abstract: A method includes providing a workpiece comprising a stack of semiconductor layers including interleaving first semiconductor layers and second semiconductor layers, forming a dummy gate structure to wrap over a channel region of the stack of semiconductor layers, performing a first etching process to selectively recess the second semiconductor layers, forming a gate spacer layer over the dummy gate structure and the stack of semiconductor layers, recessing a source/drain region of the stack of semiconductor layers to form a source/drain opening, performing a second etching process to selectively recess the second semiconductor layers from the source/drain opening to form inner spacer recesses, forming inner spacers in the inner spacer recesses, forming a source/drain feature in the source/drain opening, and replacing the dummy gate structure and the second semiconductor layers with a gate structure.

Abstract: The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T1; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness t1 on the substrate at a second temperature T2; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature T3 less than T2, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor

Abstract: Disclosed is a modified carbonaceous material, which includes hexagonal carbon networks in a layered stacking structure and acidic functional groups bonded to the hexagonal carbon networks and mainly existing at edges of the layered carbonaceous structure. Accordingly, the close proximity of acid moiety at the edges can resemble the center of hydrolysis enzymes, resulting in enhancement of hydrolytic efficiency. Additionally, the acid-functionalized carbonaceous material can also be applied in the capture and storage of carbon dioxide due to its unexpectedly higher capacity for CO2 molecular.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. The epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. The first and second type epitaxial layers are alternatingly disposed in a vertical direction. The semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. The first doped region has a first dopant of a first conductivity type. The second doped region has a second dopant of a second conductivity type opposite the first conductivity type. The semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. A portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.

Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming an epitaxial stack of channel layers and sacrificial layers on a semiconductor substrate, patterning the epitaxial stack to form a first fin-shape structure in a first region and a second fin-shape structure in a second region, etching the first fin-shape structure to form a first source/drain recess, etching the second fin-shape structure to form a second source/drain recess, forming first inner spacers in the first region, forming second inner spacers in the second region, laterally recessing the second inner spacers, forming a first source/drain feature in the first source/drain recess, and forming a second source/drain feature in the second source/drain recess. After the laterally recessing of the second inner spacers, the second inner spacers have a thickness less than the first inner spacers.

Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: A method of forming a semiconductor structure includes depositing a dummy material stack over a fin, patterning a top portion of the dummy material stack in a first etching process, patterning a middle portion of the dummy material stack in a second etching process, patterning a bottom portion of the dummy material stack in a third etching process to form a dummy gate stack, and replacing the dummy gate stack with a metal gate stack. The second etching process is weaker than the first etching process, and the third etching process is weaker than the second etching process.

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.

Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.

Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes forming a semiconductor fin over a substrate, forming an integral dielectric layer over the substrate, wherein the dielectric layer includes a first portion extending along a sidewall surface of the semiconductor fin and a second portion disposed over the semiconductor fin, a thickness of the second portion of the dielectric layer is greater than a thickness of the first portion of the dielectric layer, forming a dummy gate electrode layer over the substrate, patterning the dielectric layer and the dummy gate electrode layer to form a dummy gate structure over a channel region of the semiconductor fin, forming source/drain features coupled to the channel region of the semiconductor fin and adjacent to the dummy gate structure, and replacing the dummy gate structure with a gate stack.

Abstract: An antenna includes a ground layer, two polarization signal feeding terminals disposed on the ground layer, two polarization structures, four coupling metals and four radiating metals. The first polarization structure includes a first extending portion electrically connected to the first polarization signal feeding terminal and extends from a first channel to a second channel in a first direction over the ground layer. The second polarization structure includes a second extending portion electrically connected to the second polarization signal feeding terminal and extends from a third channel to a fourth channel in second direction over the ground layer, wherein the first extending portion crosses the second extending portion in a non-contact manner to define four regions. The four coupling metals are disposed on the first through the fourth regions, respectively. The four radiating metals are disposed on the first through the fourth channels, respectively.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. The epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. The first and second type epitaxial layers are alternatingly disposed in a vertical direction. The semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. The first doped region has a first dopant of a first conductivity type. The second doped region has a second dopant of a second conductivity type opposite the first conductivity type. The semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. A portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.

Abstract: A connecting structure includes a flexible flat cable. The flexible flat cable includes a first end portion, a second end portion, a connecting portion, a first pad region, a second pad region and a slot. The connecting portion is connected between the first end portion and the second end portion. The first pad region is disposed on the first end portion. The second pad region is disposed on the second end portion. The slot is formed in the connecting portion. The slot is extended along a length direction of the flexible flat cable. The flexible flat cable is a laminated structure including at least one set of signal trace pattern and at least one shielding structure. The at least one shielding structure correspondingly surrounds the at least one set of signal trace pattern in the connecting portion.

Abstract: Disclosed is a modified carbonaceous material, which includes hexagonal carbon networks in a layered stacking structure and acidic functional groups bonded to the hexagonal carbon networks and mainly existing at edges of the layered carbonaceous structure. Accordingly, the close proximity of acid moiety at the edges can resemble the center of hydrolysis enzymes, resulting in enhancement of hydrolytic efficiency. Additionally, the acid-functionalized carbonaceous material can also be applied in the capture and storage of carbon dioxide due to its unexpectedly higher capacity for CO2 molecular.

Abstract: The embodiments of the disclosure provide a method for operating a mirrored content under a mirror mode and a computer readable storage medium. The method includes: enabling a touch capturing function on the smart device, wherein the touch capturing function intercepts a touch event inputted to the smart device; in response to determining that a raw touch event is intercepted by the smart device, translating the raw touch event to a first touch event and sending the first touch event to a host, wherein a display screen of the smart device is mirrored to a visual content shown by the host, and the first touch event triggers the host to report a second touch event happened in the visual content; disabling the touch capturing function and receiving the second touch event from the host; and performing a first operation in response to the second touch event and enabling the touch capturing function on the smart device.