Abstract: The present disclosure discloses a pixel structure of a reflective display comprising a substrate, a shielding layer, a low reflective layer, and a reflective layer. The shielding layer is disposed on the substrate. The low reflective layer is disposed on the shielding layer. The reflective layer is disposed on the low reflective layer, wherein the reflective layer comprises a plurality of reflection regions, the plurality of reflection regions are arranged at intervals. A part of the low reflective layer is exposed between the plurality of reflection regions. In the present disclosure, the reflection of light in the gap between the pixels is avoided by the low reflective layer, such that the notice of liquid crystal disturbance by human eyes is reduced, and a reflective display with good display function and low power consumption is implemented.

Abstract: The present disclosure provides methods of forming semiconductor devices. A method according to the present disclosure includes receiving a workpiece that includes a stack of semiconductor layers, depositing a first pad oxide layer on a germanium-containing top layer of the stack, depositing a second pad oxide layer on the first pad oxide layer, depositing a pad nitride layer on the second pad oxide layer, and patterning the stack using the first pad oxide layer, the second pad oxide layer, and the pad nitride layer as a hard mask layer. The depositing of the first pad oxide layer includes a first oxygen plasma power and the depositing of the second pad oxide layer includes a second oxygen plasma power greater than the first oxygen plasma power.

Abstract: A display panel including a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer and a third metal layer is provided. The first metal layer is disposed on the substrate and includes a first storage electrode. The first insulating layer is disposed on the first metal layer. The second metal layer is disposed on the first insulating layer and includes a second storage electrode. The second insulating layer is disposed on the second metal layer. The third metal layer is disposed on the second insulating layer and includes a third storage electrode. A first storage capacitance is constituted by the first and second storage electrode as well as the first insulating layer located between thereof, and a second storage capacitance is constituted by the second and third storage electrode as well as the second insulating layer located between thereof.

Abstract: The present disclosure discloses a jump connection structure of a reflective display comprising a substrate, a shielding layer, a low reflective layer, an organic layer, a first transparent conductive layer, and a first reflective layer. The shielding layer is disposed on the substrate. The low reflective layer is disposed on the shielding layer. The organic layer is disposed on the low reflective layer, wherein the organic layer and the low reflective layer have a first via, and a part of the shielding layer is exposed from the first via. The first transparent conductive layer is disposed on the exposed shielding layer. The first reflective layer is disposed on a top surface of the organic layer, a side surface of the organic layer, and the first transparent conductive layer. In the present disclosure, a reflective display with good display function and low power consumption is implemented by the jump connection structure.

Abstract: The present invention discloses a dielectric filter with multilayer resonator, including a dielectric block, a plurality of multilayer resonator formed in the dielectric block, wherein each multilayer resonator is in a column shape extending in a first direction into the dielectric block and is formed of multiple metal layers paralleling and overlapping each other in a second direction, and vias extend in the second direction and connecting the metal layers in each multilayer resonator, and a ground electrode connected to the ground terminal of each multilayer resonator.

Abstract: Methods and associated devices including the fabrication of a semiconductor structure are described that include epitaxially growing a stack of layers alternating between a first composition and a second composition. The stack of layers extends across a first region and a second region of a semiconductor substrate. The stack of layers in the second region of the semiconductor substrate may be etched to form an opening. A passivation process is then performed that includes introducing chlorine to at least one surface of the opening. After performing the passivation process, an epitaxial liner layer is grown in the opening.

Abstract: A antenna structure including a reflector, a horizontally polarized antenna and a vertically polarized antenna on the front side of reflector, wherein the horizontally polarized antenna is made up of a pair of dipoles, each said dipole includes a positive ground member and a negative ground member overlapping each other, while the vertically polarized antenna is made of a upper ground member and a lower ground member overlapping each other, and the upper ground member is above the upper dipole and the lower ground member is below the lower dipole, and a first signal source and a second signal source extend from the back side of the reflector to the front side to excite the horizontally polarized antenna and the vertically polarized antenna, respectively.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a structure having a frontside and a backside, the structure including a substrate and a stack of a first type and a second type epitaxial layers having different material compositions alternatively stacked above the substrate, wherein the stack is at the frontside of the structure and the substrate is at the backside of the structure; patterning the stack, thereby forming a fin above the substrate; implanting a first dopant into a first region of the fin, the first dopant having a first conductivity type; implanting a second dopant into a second region of the fin, the second dopant having a second conductivity type opposite the first conductivity type; and forming a first contact on the first region and a second contact on the second region.

Abstract: The present invention discloses a turning air mattress, a turning air cell, and a control method for a turning air mattress. With structural arrangements of an upper portion and a lower portion of the turning air cell as well as inflation and deflation control, the turning air cell having an upper portion that is wider and a lower portion that is narrower can further assist a patient in body turning, enabling the patient to easily achieve a sufficient body turning angle, further reducing the risk of likeliness to pressure sores caused by the structure of the air mattress pressing against the body of the patient.

Abstract: A front electrode layer of a thin film solar cell is provided. The front electrode layer includes a first transparent conductive layer and a second transparent conductive layer. The first transparent conductive layer is disposed on a substrate, and the second transparent conductive layer is disposed on the first transparent conductive layer, wherein the first transparent conductive layer is located between the substrate and the second transparent conductive layer, and wherein a surface roughness of the second transparent conductive layer is lower than a surface roughness of the first transparent conductive layer.

Abstract: A manufacturing method of a front electrode layer of a thin film solar cell including steps below is provided. First, a first transparent conductive layer having a plurality of microstructures is formed on a substrate. Then, a second transparent conductive layer is formed on a surface having the plurality of microstructures of the first transparent conductive layer. A front electrode layer of a thin film solar cell is also provided.

Abstract: A photoelectric display unit including a bottom electrode layer, a photoelectric conversion layer and a top electrode layer is provided. The photoelectric conversion layer is disposed between the bottom electrode layer and the top electrode layer, and includes a first extrinsic semiconductor layer, an intrinsic semiconductor layer and a second extrinsic semiconductor layer. The intrinsic semiconductor layer is disposed between the first extrinsic semiconductor layer and the second extrinsic semiconductor layer. The intrinsic semiconductor layer includes a semiconductor material with a range of a band gap of 1.7 ev˜3.2 ev.

Abstract: A delay circuit includes a delay line including at least a first group of delay elements. The delay line is responsive to a first digital delay code to delay an input signal by a first delay value, and responsive to a change from the first digital delay code to a second digital delay code to delay the input signal by a second delay value. Control circuitry generates the first and second digital delay codes. Glitch monitoring circuitry couples to the control circuitry to conditionally gate the change from the first digital delay code to the second digital delay code based on a prediction of a glitch condition.

Abstract: A manufacturing method of a display panel including following steps is provided. Providing a substrate. Forming a first metal layer including a first storage electrode on the substrate. Forming a first insulating layer on the first metal layer. Forming a second metal layer including a second storage electrode on the first insulating layer. Forming a second insulating layer on the second metal layer. Forming a third metal layer including a third storage electrode on the second insulating layer. A first storage capacitance is constituted by the first storage electrode and the second storage electrode as well as the first insulating layer located between the first storage electrode and the second storage electrode, and a second storage capacitance is constituted by the second storage electrode and the third storage electrode as well as the second insulating layer located between the second storage electrode and the third storage electrode.

Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.

Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.

Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further incudes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.

Abstract: A delay balancing circuit includes a phase detection circuit, a controller, and a delay circuit. The phase detection circuit receives a reference clock signal having a first frequency, and a feedback clock signal derived from an output clock signal. Detection circuitry detects a phase relationship between the reference clock signal and the feedback clock signal. The phase detection circuit generates a detection signal based on the detected phase relationship. The controller operates to sample the detection signal and to generate and pass an update signal to a delay line to update a delay based on the sampled value. The delay circuit receives a third clock signal and applies a delay, based on the update signal, to the third clock signal to generate the output clock signal.

Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.