Abstract: A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Abstract: A mechanism for facilitating cost-efficient and low-latency video stream encoding for limited channel bandwidth is described. In one embodiment, an apparatus includes a source device having an encoding logic. The encoding logic may include a first logic to receive a video stream having a plurality of video frames. The video stream is received frame-by-frame. The encoding logic may further include a second logic to determine an input data rate relating to a first current video frame of the plurality of video frames received at the encoding mechanism, and a third logic to generate one or more zero-delta frames based on the input data rate, and allocate the one or more zero-delta frames to one or more first video frames of the plurality of video frames subsequent to the first current video frame.

Abstract: Embodiments of the invention describe a multimedia stream switch capable of multiplexing the audio and the video data of a multimedia stream separately. The multiplexing features of embodiments of the invention enable a multimedia stream switch to control each multimedia data type separately instead of multiplexing the whole streams (i.e., multiplexing sets of audio/video data together). Furthermore, prior art multimedia stream switches need to regenerate audio clocks by using phase locked loop (PLL) circuitry which incurs manufacturing and development costs. Embodiments of the invention provide the mixing of audio and video data from different sources without the need for PLL circuitry.

Abstract: Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time.

Abstract: An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects an edge of received data and recovers the data using a time difference between a reference point of the reference clock and the detected edge.

Abstract: Embodiments of the invention are generally directed to a multimedia I/O system architecture for advanced digital television. An embodiment of a multimedia system includes an I/O (input/output) control chip, the I/O control chip including one or more audio/video sub-processing engines for the processing of one or more data streams; a processing core chip for the processing of data, including audio/video data received from the I/O control chip; and one or more shared I/O channels for the transfer of data between the I/O control chip and the processing core chip.

Abstract: An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line.

Abstract: A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Abstract: An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line.

Abstract: Semiconductor apparatuses having optical connections between a memory controller and a memory module are provided. A semiconductor apparatus includes a memory controller, at least one socket configured to receive a memory module, and a first optical-electrical module. A second optical-electrical module is mounted in the socket and optically coupled to the first optical-electrical module via at least one optical channel.

Abstract: An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects an edge of received data and recovers the data using a time difference between a reference point of the reference clock and the detected edge.

Abstract: A system, method and article of manufacture are provided for updating a switching table in a switch fabric. In general, one or more status packets are received by a switch fabric component without handshaking between the transmitting source(s) and the receiving switch fabric component. Each status packet includes information relating to a status of an output port. A switching table is then updated based on the status information of the received status packet.

Abstract: A system, method and article of manufacture are provided for updating a switching table in a switch fabric. In general, one or more status packets are received by a switch fabric component without handshaking between the transmitting source(s) and the receiving switch fabric component. Each status packet includes information relating to a status of an output port. A switching table is then updated based on the status information of the received status packet.