Patents by Inventor Ju Liang

Ju Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11605543
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Publication number: 20230041859
    Abstract: The present invention relates to a method of preventing or treating a fibrotic condition, comprising administering an effective amount of composition to a subject in need thereof; wherein the composition comprises triterpenes extracted from Antrodia camphorate or Anisomeles indica.
    Type: Application
    Filed: July 1, 2021
    Publication date: February 9, 2023
    Inventors: Yeh-B WU, Jir-Mehng LO, Hui-Ju LIANG, Pei-Hsin LIN, Kuo-Kuei HUANG
  • Publication number: 20230019633
    Abstract: A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.
    Type: Application
    Filed: May 5, 2022
    Publication date: January 19, 2023
    Inventors: Yi-Cheng Li, Pin-Ju Liang, Ta-Chun Ma, Pei-Ren Jeng, Yee-Chia Yeo
  • Patent number: 11532911
    Abstract: A connecting device and an assembly of the connecting device and a mating device are provided. The connecting device includes an insulating main body, a plurality of terminals, a magnet set, an inner housing, a crown leaf spring, an outer housing, and a wave spring. The plurality of terminals are disposed on the insulating main body, the magnet set is disposed on the insulating main body, and the inner housing is sleeved around the insulating main body. The wave spring and the crown leaf spring are each disposed between the inner housing and the outer housing, and abut the inner housing, so that the insulating main body, the plurality of terminals, the magnet set, and the inner housing are arranged in a floating state.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: December 20, 2022
    Assignee: NEXTRONICS ENGINEERING CORP.
    Inventors: Yong Zhang, Liang-Ju Liang
  • Publication number: 20220376091
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Ju LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Publication number: 20220320796
    Abstract: A connecting device and an assembly of the connecting device and a mating device are provided. The connecting device includes an insulating main body, a plurality of terminals, a magnet set, an inner housing, a crown leaf spring, an outer housing, and a wave spring. The plurality of terminals are disposed on the insulating main body, the magnet set is disposed on the insulating main body, and the inner housing is sleeved around the insulating main body. The wave spring and the crown leaf spring are each disposed between the inner housing and the outer housing, and abut the inner housing, so that the insulating main body, the plurality of terminals, the magnet set, and the inner housing are arranged in a floating state.
    Type: Application
    Filed: July 13, 2021
    Publication date: October 6, 2022
    Inventors: Yong Zhang, Liang-Ju Liang
  • Publication number: 20220310783
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
  • Publication number: 20220236588
    Abstract: An eyeglasses assembly structure is revealed. A pivot member which is pivotally connected to a first assembly portion of a frame is inserted and mounted in a switch member. A first rib and a second rib are opposite to each other and disposed on a second assembly portion at a front side of a temple. The first rib is mounted into a first mounting groove at one end of the pivot member. A positioning flange is formed on the second rib and inserted through an opening of the switch member to be mounted in a second mounting groove on the other end of the pivot member. When the switch member is rotated an angle to be staggered or aligned with respect to the positioning flange of the second rib, the temple is firmly fixed to or separated from the frame. Thereby parts are assembled and replaced easily and conveniently.
    Type: Application
    Filed: November 19, 2021
    Publication date: July 28, 2022
    Inventor: JU-LIANG CHENG
  • Publication number: 20220172958
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 11289343
    Abstract: A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Chia-Ao Chang, Pin-Ju Liang
  • Patent number: 11253527
    Abstract: The present invention pertains to a composition for preparing a medicament for preventing and/or treating a virus infection, especially a hepatitis B virus infection and/or a herpes simplex virus, and uses thereof.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 22, 2022
    Assignee: ARJIL BIOTECH HOLDING COMPANY LIMITED
    Inventors: Yeh B Wu, Jir-Mehng Lo, Hui Ju Liang, Pei-Hsin Lin, Cheng Huang
  • Patent number: 11232988
    Abstract: Methods of rectifying a sidewall profile of a fin-shaped stack structure are provided. An example method includes forming, on a substrate, a first fin-shaped structure and a second fin-shaped structure each including a plurality of channel layers interleaved by a plurality of sacrificial layers; depositing a first silicon liner over the first fin-shaped structure and the second fin-shaped structure; depositing a dielectric layer over the substrate, the first fin-shaped structure and the second fin-shaped structure; etching back the dielectric layer to form an isolation feature between the first fin-shaped structure and the second fin-shaped structure and to remove the first silicon liner over the first fin-shaped structure and the second fin-shaped structure to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and epitaxially depositing a second silicon liner over the exposed sidewalls of the plurality of channel layers and the plurality of sacrificial layers.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Wen Shen, You-Ting Lin, Jiun-Ming Kuo, Yuan-Ching Peng, Yi-Cheng Li, Pin-Ju Liang, Pei-Ren Jeng
  • Patent number: 11196218
    Abstract: A connector with a direct locking and a rotational pre-ejection function is provided. The connector includes an insulated body, a plurality of terminals, an inner shell, an outer shell, a fastener, an ejector, a first elastic element, and a second elastic element. A plurality of push blocks are disposed in the outer shell, the ejector has a plurality of slope surfaces, and the push blocks are in contact with the slope surfaces, respectively. When the connector and a mating connector are inserted into each other, snap bodies of the fastener and fastener bodies of the mating connector can be snapped into each other to be directly locked. When the connector and the mating connector are to be separated from each other, the outer shell can be rotated to cause the snap bodies to disengage and to cause the push blocks to rotate while in contact with the sloped surfaces to effect ejector rods to move forwardly to eject the mating connector.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 7, 2021
    Assignee: NEXTRONICS ENGINEERING CORP.
    Inventors: Hou-An Su, Frank Hsu, Wen-Feng Xie, Can-Hui Liang, Liang-Ju Liang, Yong Zhang
  • Publication number: 20210375688
    Abstract: Methods of rectifying a sidewall profile of a fin-shaped stack structure are provided. An example method includes forming, on a substrate, a first fin-shaped structure and a second fin-shaped structure each including a plurality of channel layers interleaved by a plurality of sacrificial layers; depositing a first silicon liner over the first fin-shaped structure and the second fin-shaped structure; depositing a dielectric layer over the substrate, the first fin-shaped structure and the second fin-shaped structure; etching back the dielectric layer to form an isolation feature between the first fin-shaped structure and the second fin-shaped structure and to remove the first silicon liner over the first fin-shaped structure and the second fin-shaped structure to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and epitaxially depositing a second silicon liner over the exposed sidewalls of the plurality of channel layers and the plurality of sacrificial layers.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Shu-Wen Shen, You-Ting Lin, Jiun-Ming Kuo, Yuan-Ching Peng, Yi-Cheng Li, Pin-Ju Liang, Pei-Ren Jeng
  • Publication number: 20210366715
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
  • Publication number: 20210359111
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 18, 2021
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Ju LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Patent number: 11176143
    Abstract: Among other things, one or more techniques and/or systems are provided for location-aware content detection. In particular, content may be grouped into topic clusters (e.g., images, articles, and/or websites may be grouped into a football cluster, an earthquake cluster, etc.). A topic of a cluster may be assigned a global ranking (e.g., based upon an importance of a topic on a global scale) and/or local rankings for local regions (e.g., based upon importance of a topic to various local regions). A local ranking may be based upon user interaction with content associated with the topic (e.g., many users from Japan may be reading about the earthquake). In this way, content may be provided to users based upon global rankings and/or local rankings (e.g., content from around the world about the earthquake may be presented to users in Japan and/or other areas that have expressed interest in the earthquake).
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: November 16, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bangyong Liang, Ju Liang, Jin Jiang, Xiaosong Yang
  • Publication number: 20210338690
    Abstract: The present invention pertains to anti-coronaviral compounds. The disclosure includes a method for preventing and/or treating a coronavirus infection through the inhibition of a cysteine protease in a virus, particularly SARS-COV-2. Also provided includes the composition/pharmaceutical composition for preventing and/or treating a coronavirus infection comprising any of the compounds, pharmaceutically acceptable salt thereof, or its mixture, and the use of the compounds.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 4, 2021
    Applicant: ARJIL BIOTECH HOLDING COMPANY LIMITED
    Inventors: Jir-Mehng LO, Cheng HUANG, Yeh B WU, Hui-Ju LIANG, Pei-Hsin LIN, Hao CHIANG, Wei-Chung CHIOU
  • Patent number: 11107903
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Pin-Ju Liang, I-Chen Yang
  • Patent number: 11087987
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen