Patents by Inventor Ju Wu

Ju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240085802
    Abstract: Some implementations described herein provide an exposure tool. The exposure tool includes a reticle deformation detector and one or more processors configured to obtain, via the reticle deformation detector, reticle deformation information associated with a reticle during a scanning process for scanning multiple fields of a wafer. The one or more processors determine, based on the reticle deformation information, a deformation of the reticle at multiple times during the scanning process, and perform, based on the deformation of the reticle at the multiple times, one or more adjustments of one or more components of the exposure tool during the scanning process.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Min-Cheng WU, Ching-Ju HUANG
  • Publication number: 20240087980
    Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Yen-Pin HSU, Li-Ling SU, Ming-Hsien LIN, Hsiao-Kang CHANG
  • Patent number: 11929409
    Abstract: Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; a
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Ju Lee, Chun-Fu Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11927303
    Abstract: A wearable device includes a host, a first belt, a second belt, a circuit board, a cable, and an adjustment mechanism. The first belt, one end of which is connected to a first side of the host, has a cable holding part. One end of the second belt is connected to a second side of the host. The circuit board is disposed at an overlap of the first belt and the second belt. A first end and a second end opposite to each other of the cable are connected to the circuit board and the first side respectively, and a holding section of the cable is fixed to the cable holding part. The adjusting mechanism is disposed at an overlap of the first belt and the second belt to adjust an overlapping length of the first belt and the second belt.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 12, 2024
    Assignee: HTC Corporation
    Inventors: Tsen-Wei Kung, Chung-Ju Wu, Tsung Hua Yang, Chih-Yao Chang, Wei Te Tu
  • Patent number: 11923888
    Abstract: Embodiments of this application disclose a full-duplex self-interference cancellation method and apparatus. The full-duplex self-interference cancellation method may be applied to the field of radio frequency self-interference cancellation in a full-duplex scenario. The full-duplex self-interference cancellation method is implemented by a full-duplex self-interference cancellation apparatus with self-interference reconstruction modules of two levels, and the full-duplex self-interference cancellation apparatus is implemented by a terminal. This greatly reduces hardware implementation complexity and costs of the second self-interference reconstruction module, and improves a full-duplex self-interference cancellation capability.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Teyan Chen, Ju Cao, Tao Wu
  • Patent number: 11923205
    Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
  • Publication number: 20240065765
    Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: Alvin Chao-Yu CHEN, Yi-Sheng CHAN, Chi-Pin HSU, Shang-Chih LIN, Chin-Ju WU, Jeng-Ywan JENG
  • Patent number: 11914941
    Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
  • Publication number: 20240038665
    Abstract: An interconnection structure is provided to include an interlayer dielectric (ILD) layer that is disposed over a substrate, a metal via that is disposed in the ILD layer, and a metal wire that is disposed over the metal via in the ILD layer and that is electrically connected to the metal via. The ILD layer includes silicon carbon nitride.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Yen-Ju WU, Hsiao-Kang CHANG
  • Publication number: 20240038666
    Abstract: A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes a dielectric layer, an interconnect structure disposed in the dielectric layer, and an etch stop layer which is disposed on a lower end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of SixCyNz, wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Cheng-Chin LEE, Yen-Ju WU, Hsin-Yen HUANG, Hsiao-Kang CHANG
  • Patent number: 11874313
    Abstract: A probe card and a manufacturing method of a probe card are provided. The probe card includes a probe head, first and second substrates, a first elastic component, and a first adhesive member. The second substrate is disposed between the probe head and the first substrate, and is disposed on the first substrate. The second substrate faces the first substrate and includes second contacts. The second contacts are electrically connected to first contacts of the first substrate. The first elastic component is disposed between the first substrate and the second substrate, and disposed at an outer side of the second contacts. The first adhesive member is disposed on the first substrate, annularly arranged on the side surface of the second substrate, and disposed at an outer side of the first elastic component.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: January 16, 2024
    Assignee: MPI CORPORATION
    Inventors: Chin-Yi Lin, Che-Wei Lin, Ting-Ju Wu, Chien-Kai Hung
  • Publication number: 20240000649
    Abstract: A patient brace system and method of using the same are disclosed for treatment of lower extremity injuries. Described brace systems include a crutch, at least one crutch sensor, a patient brace, at least one controller, and a rehabilitation application. The crutch sensor(s) measure one or more crutch parameters. The controller(s) are operable to receive and process a signal(s) indicative of the crutch parameter(s) and produces patient gait data that, in turn, is communicated to a data hub. In some embodiments, the patient brace may also include at least one brace sensor configured to similarly communicate with the data hub. The rehabilitation application is communication with the data hub and determines a response output based on the information fed to the data hub, the application then communicating the response output to at least one of a caregiver, a user of the patient brace, and/or to the patient brace.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: David B. Spenciner, Cheng-Ju Wu, Drew Miller, Steven Nguyen, Ravi Patel
  • Patent number: 11852673
    Abstract: Provided is a method for generating a chip probing wafer map, and the method includes: obtaining test data associated with a first chip, wherein the first chip includes a plurality of sequentially arranged first dies, and each of the first dies belongs to one of a plurality of bin numbers; assigning different predetermined color codes to the bin numbers; and generating a first general chip probing wafer map for the first chip by assigning a color code of each of the first dies as a corresponding predetermined color code according to the bin number to which each of the first dies belongs.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: December 26, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Ju Wu, Ching-Ly Yueh
  • Patent number: 11844187
    Abstract: A cable management device in a server chassis able to hold and safeguard a greatly extended range of cable lengths, and server chassis including same, comprises connecting assembly, sliding rail assembly, and cable management assembly. The sliding rail assembly includes parallel first and second sliding rails, the first sliding rail including outer, middle, and inner rails, and the second sliding rail including similar outer, middle, and inner rails. The assembly includes first to fourth sliding arms, together with a supporting bar. The first sliding arm is movably connected to the outer rail of the second sliding rail, and the fourth sliding arm is movably connected to the inner rail of the first sliding rail. One end of the supporting bar is connected to the middle rail of the first sliding rail, the other end is connected to the middle rail of the second sliding rail.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: December 12, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Chang-Ju Wu, Chen-Sheng Tang
  • Patent number: 11832754
    Abstract: A lid structure, which is used for covering an opening of a container, includes a mainbody, an elastic annular element, and a covering assembly. The mainbody includes a through hole. The elastic annular element is integrally disposed on a peripheral region of the mainbody, wherein the elastic annular element is used for positioning the lid structure on the opening. The covering assembly is disposed on the mainbody and includes a spacer element and a covering element. The spacer element is disposed on and covers the through hole. The spacer element includes a plurality of drain holes and a central connecting portion. The covering element is deformably disposed on the central connecting portion.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: December 5, 2023
    Assignee: CHANG YANG MATERIAL CO., LTD.
    Inventors: Ming Hua Huang, Lung Hsun Song, Yun Ju Wu, Hung Yu Hsieh, Lin Chun Sun
  • Publication number: 20230376543
    Abstract: A computer-implemented system and method for analyzing clusters of coded documents is provided. Clusters of documents are displayed and at least a portion of the documents are each associated with a classification code. A representation of each document is provided based on the associated classification code or an absence of the associated classification code. A search query with search terms is received. Each search term is associated with one of the classification codes. Those documents that satisfy the search query are identified and the representations of the identified documents are changed based on the classification codes associated with the search terms. The change in representation provides an indication of agreement between the classification code of such document and the classification codes of the search terms, or an indication of disagreement between the classification code of the document and the classification codes of the search terms.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Joe Milan, Eric Robinson, David Stromberg, Collin Arnold, Shiow Ju Wu
  • Patent number: 11821952
    Abstract: A method of estimating a d-q axis inductance of a permanent magnet synchronous motor includes the following steps. First, building an equivalent motor control block through enabling two of the three phases, and disabling the remaining one of the three phases, and locking a rotor. Afterward, incorporating a back EMF observer into a DC motor control block, and making the DC motor control block correspond to the back EMF observer by commanding an angular speed of the DC motor control block to be zero. Afterward, introducing the equivalent motor control block into the DC motor control block, and using the back EMF observer to estimate the back EMF, and repeating above steps taking turns to disable one phase so as to obtain three sets of motor inductances respectively. Finally, estimating the d-q axis inductance by introducing the three sets of equivalent motor inductances into an inductance relational equation.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 21, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Mi-Ching Tsai, Ting-Chung Hsieh, Lung-Jay Cheng, Yao-Sheng Wu, Chun-Ju Wu
  • Publication number: 20230316560
    Abstract: A tracking apparatus, method, and non-transitory computer readable storage medium thereof are provided. The tracking apparatus generates a map information of simultaneous localization and mapping corresponding to a regional space based on a real-time image. The tracking apparatus calculates a first spatial position and a first orientation of a first display related to the image capturing device in the regional space based on the map information. The tracking apparatus calculates a human pose of a first operating user in the regional space. The tracking apparatus transforms the real-time image to generate a first transformed image corresponding to the first operating user based on the first spatial position, the first orientation, and the human pose, wherein the first transformed image is displayed on the first display.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 5, 2023
    Inventors: Yen-Ting LIU, Meng-Ju WU
  • Patent number: D1018524
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: March 19, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jyh-Chyang Tzou, Shi-Kuan Chen, I Ta Tsai, Meng Ju Wu