Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

Abstract: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Abstract: A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.