Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

Abstract: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Abstract: A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Abstract: A semiconductor memory device includes a substantially planar substrate, a memory string vertical to the substrate, the memory string comprising a plurality of storage cells, and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Abstract: An InSb-based switching device, which operates at room temperature by using a magnetic field controlled avalanche process for applying to magneto-logic elements, is provided. A switching device of one embodiment includes a p-type semiconductor layer; an n-type semiconductor layer; and contact layers disposed on one of the p-type and n-type semiconductor layers, the p-type semiconductor layer being in contact with the n-type semiconductor layer such that a current can be applied through the contact layers to the p-type and n-type semiconductor layers to cause a current flow from one of the contact layers to the p-type and n-type semiconductor layers and from the p-type and n-type semiconductor layers to the other of the contact layers, whereby the current flow can be controlled by an intensity of a magnetic field applied to the p-type and n-type semiconductor layers substantially perpendicularly thereto.

Abstract: A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

Abstract: A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings.

Abstract: A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.

Abstract: The present invention provides an InSb-based switching device operating at room temperature by using a magnetic field controlled avalanche process for applying to magneto-logic elements. A switching device of one embodiment includes a p-type semiconductor layer; an n-type semiconductor layer; and contact layers disposed on one of the p-type and n-type semiconductor layers, the p-type semiconductor layer being in contact with the n-type semiconductor layer such that a current can be applied through the contact layers to the p-type and n-type semiconductor layers to cause a current flow from one of the contact layers to the p-type and n-type semiconductor layers and from the p-type and n-type semiconductor layers to the other of the contact layers, whereby the current flow can be controlled by an intensity of a magnetic field applied to the p-type and n-type semiconductor layers substantially perpendicularly thereto.

Abstract: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

Abstract: A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings.

Abstract: Disclosed is a method of manufacturing a semiconductor device whereby InAs(1-x)Sbx semiconductor layer is formed on an easily available and economical semiconductor substrate such as a GaAs substrate or a Si substrate. According to the method, a quantum dot layer is formed between a semiconductor substrate and a semiconductor layer to reduce defects caused by lattice mismatch between the semiconductor layer and the semiconductor layer. The method may improve the growth speed of the semiconductor layer. In addition, because the InSb layer provided by the present invention has an electron mobility greater at room temperature, it may improve the quality and productivity of the semiconductor device.

Abstract: A semiconductor memory device and method of manufacturing the same are disclosed. The semiconductor memory device includes a semiconductor substrate having a cell region and a peripheral circuit region, first transistors provided on the semiconductor substrate, a first semiconductor layer provided on the first transistors, and bonded by a bonding technique, and second transistors provided on the first semiconductor layer, wherein the first and second transistors are provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer, respectively, and a metal layer is formed on gates of the first and second transistors respectively provided in the peripheral circuit regions of the semiconductor substrate and the first semiconductor layer. As a result, the transistors in the peripheral circuit region requiring high performance can be formed on an upper layer and a lower layer.

Abstract: Disclosed is a method of manufacturing a semiconductor device whereby InAs(1-x)Sbx semiconductor layer is formed on an easily available and economical semiconductor substrate such as a GaAs substrate or a Si substrate. According to the method, a quantum dot layer is formed between a semiconductor substrate and a semiconductor layer to reduce defects caused by lattice mismatch between the semiconductor layer and the semiconductor layer. The method may improve the growth speed of the semiconductor layer. In addition, because the InSb layer provided by the present invention has an electron mobility greater at room temperature, it may improve the quality and productivity of the semiconductor device.