Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

Abstract: Methods of magnetically shielding a perpendicular STT-MRAM structure on all six sides within a flip-chip package and the resulting devices are provided. Embodiments include forming a passivation stack over an upper surface of a wafer and outer portions of an Al pad; forming a polymer layer over the passivation stack; forming a UBM layer over the Al pad, portions of the polymer layer and along sidewalls of the polymer layer; forming a T-shaped Cu pillar over the UBM layer; forming a ?-bump over the T-shaped Cu pillar; dicing the wafer into a plurality of dies; forming an epoxy layer over a bottom surface of each die; forming a magnetic shielding layer over the epoxy layer and along sidewalls of each die, the epoxy layer, the passivation stack and the polymer layer; and connecting the ?-bump to a package substrate with a BGA balls.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: A scalable method of forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJs and the resulting devices are provided. Embodiments include providing a Si substrate of an X-density STT-MRAM having an array of interconnect stacks; forming a level of a MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein (X?1) defines a number of interconnect stacks between the first and the second interconnect stacks; forming a via on each interconnect stack without a MTJ structure; forming a metal layer on each MTJ structure and via on the level; repeating the forming of the MTJ structure, the via, and the metal layer one interconnect stack laterally shifted until the level of the MTJ structure equals X, only forming the MTJ structure at that level; forming a bit line over the substrate; and connecting the bit line to each MTJ structure.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

Abstract: High density resistive memory structures, integrate circuits with high density resistive memory structures, and methods for fabricating high density resistive memory structures are provided. In an embodiment, a high density resistive memory structure includes a semiconductor substrate and a plurality of first electrodes in a first plane in and/or over the semiconductor substrate. Further, the high density resistive memory structure includes a plurality of second electrodes in a second plane in and/or over the semiconductor substrate. The second plane is parallel to the first plane, and each second electrode in the plurality of second electrodes crosses over or under each first electrode in the plurality of first electrodes at a series of cross points. Each second electrode in the plurality of second electrodes is non-linear and the series of cross points formed by each respective second electrode is non-linear.

Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate having a buried insulator layer and an active layer overlying the buried insulator layer. A transistor overlies the buried insulator layer, and a memory cell underlies the buried insulator layer. As such, the memory cell and the transistor are on opposite sides of the buried insulator layer.

Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

Abstract: Devices are formed to have inner layers that have electronic devices, and an outer passivation layer. A patterned conductor is formed on a first surface of the inner layers, and through conductors (that extend through interior insulator layers) are positioned to electrically connect the patterned conductor to the electronic devices. The patterned conductor includes a pattern of connected linear sections that are parallel to the first surface of the inner layers. The linear sections of the patterned conductor meet at conductor corners, and at least one of the conductor corners of the patterned conductor includes a chamfer side that terminates at the linear sections. Further, the chamfer side is not perfectly diagonal, but instead forms unequal angles with the linear sections that intersect to form the corner.

Abstract: A method of forming a stop layer to prevent dummy vias from connecting to a metal layer and the resulting device are provided. Embodiments include forming a first metal layer in a first dielectric layer; forming a second dielectric layer over a first Nblok layer formed over the first dielectric and first metal layers; forming a third dielectric layer over the second dielectric layer and a second Nblok layer formed over a portion of the second dielectric layer; forming a via and a plurality of vias through the third and second dielectric layers down to the second and first Nblok layers, respectively; removing portions of the second and first Nblok layers through the via and the plurality of vias down to the second dielectric layer and the first metal layer, respectively; removing portions of the third dielectric layer through each via; and filling each via with a second metal layer.

Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.

Abstract: Devices and methods for forming a device are disclosed. At least one die is provided. A redistribution layer having a fan-out region extends concentrically outwards from an outer perimeter of the at least one die. A seal ring is disposed in the fan-out region of the redistribution layer.

Abstract: A seal ring structure is disclosed for integrated circuit (IC) packaging. The seal ring includes an inner moisture barrier ring and an outer crack stop ring. Line structures of both the inner and outer rings include chamfered corners. The chamfers of a chamfered corner are devoid of acute angles. No metal line structure for the inner ring is provided at the pad level. The seal ring as described improves the reliability and strength of the structure and hence the seal ring can sustain high stress at the corners of the die during dicing.