Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.

Abstract: Structures for an optoelectronic memory and related fabrication methods. A metal oxide layer is located on an interlayer dielectric layer. A layer composed of a donor/acceptor dye is positioned on a portion of the first layer.

Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.

Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

Abstract: The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.

Abstract: The disclosed subject matter relates to a structure and method to improve bond pad reliability of semiconductor devices. According to an aspect of the present disclosure, a bond pad structure is provided that includes a dielectric layer and at least one bond pad in the dielectric layer, wherein the bond pad has a top surface. A passivation layer has an opening over the bond pad, wherein the opening has sidewalls. A low-k barrier layer is covering the sidewalls of the opening and the top surface of the bond pad. Protective structures are formed over the sidewalls of the opening.

Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.

Abstract: A device and methods for forming the device is provided. The device includes a substrate and circuit elements thereon. The device further includes a metallization layer over the substrate. The metallization layer includes interconnects interconnecting the circuit elements. A test pad is disposed over an uppermost interconnect in the metallization layer. The test pad is coupled to one or more circuit elements via the interconnects. The test pad is configured for testing the one or more circuit elements. A crack stop protection seal surrounding the test pad is provided. The crack stop protection seal confines damage caused by probing at the test pad from propagating to an area beyond the crack stop protection seal.

Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

Abstract: Integrated circuits with integrated memory devices and high capacitors, and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming, from a lower conductive layer, a lower memory interconnect and a lower capacitor interconnects over a substrate. The method further includes forming a conductive memory via coupled to the lower memory interconnect and a conductive capacitor vias coupled to the lower capacitor interconnect. Also, the method includes forming a memory structure over the memory via and forming a capacitor dielectric layer over the memory structure and over the capacitor via. Further, the method includes forming, from an upper conductive layer, an upper memory interconnect coupled to the memory structure and an upper capacitor interconnects over the capacitor dielectric layer over the capacitor via. The capacitor via, capacitor dielectric layer, and upper capacitor interconnects form the high capacitor.

Abstract: A device including a capping layer over a portion of a top electrode, and method of production thereof. Embodiments include an MRAM cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell includes a MTJ pillar between a top electrode and a bottom electrode; and a capping layer over a portion of the top electrode.

Abstract: Integrated circuits with integrated memory devices and high capacitors, and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming, from a lower conductive layer, a lower memory interconnect and a lower capacitor interconnects over a substrate. The method further includes forming a conductive memory via coupled to the lower memory interconnect and a conductive capacitor vias coupled to the lower capacitor interconnect. Also, the method includes forming a memory structure over the memory via and forming a capacitor dielectric layer over the memory structure and over the capacitor via. Further, the method includes forming, from an upper conductive layer, an upper memory interconnect coupled to the memory structure and an upper capacitor interconnects over the capacitor dielectric layer over the capacitor via. The capacitor via, capacitor dielectric layer, and upper capacitor interconnects form the high capacitor.

Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contacts formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.

Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.

Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.

Abstract: Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming from a first metallization layer a first lower conductive interconnect in a first region of a dielectric layer and a second lower conductive interconnect in a second region of the dielectric layer. The method includes forming a memory structure in the first region. Further, the method includes depositing an interlayer dielectric over the first region and over the second region. Also, the method includes forming from a second metallization layer a first upper conductive interconnect over the interlayer dielectric, wherein the first upper conductive interconnect is coupled to the memory structure.

Abstract: According to an aspect of the present disclosure, a semiconductor device is provided that includes a substrate, at least one bond pad, a passivation layer and a NBLoK layer. The bond pad is formed over the substrate. The passivation layer is deposited over the substrate and has an opening defined by end portions of the passivation layer over the bond pad. The NBLoK layer is covering the end portions of the passivation layer.

Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.

Abstract: A method of forming an integrated circuit with a metal-insulator-poly (MIP) capacitor formed in a high-k metal gate (HKMG) process and the resulting device are provided. Embodiments include a device including a metal gate; a high-k dielectric layer formed around side walls of the metal gate, and a dummy polysilicon gate adjacent to at least one portion of the high-k dielectric layer. The device also includes a capacitor including the HK layer as an insulator, wherein the insulator is between a dummy as one electrode and the metal gate as another electrode.

Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contact formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.