Patents by Inventor Juan-Carlos Calderon

Juan-Carlos Calderon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8018926
    Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: September 13, 2011
    Inventors: Jing Ling, Soowan Suh, Juan-Carlos Calderon
  • Publication number: 20110126074
    Abstract: A method of manufacture a transport network system includes: receiving input data having an input encoding; generating encoded data, having a transcode encoding, from the input data; generating an error correction redundancy for the encoded data; and sending an output frame, having the encoded data and the error correction redundancy, for increasing a net coding gain of the output frame based on the transcode encoding and the error correction redundancy.
    Type: Application
    Filed: November 24, 2009
    Publication date: May 26, 2011
    Applicant: CORTINA SYSTEMS, INC.
    Inventors: Juan-Carlos Calderon, Arun Zarabi, Jean-Michel Caia
  • Patent number: 7656891
    Abstract: A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises interleaving data in a predetermined format and controlling distribution of the data irrespective of the format received such that the data can be processed at the destination and passed to downstream components.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Soowan Suh, Jing Ling, Jean-Michel Caia, Alejandro Lenero Beracoechea
  • Patent number: 7606269
    Abstract: A method and apparatus for determining a loss of alignment defect in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise performing specific evaluations and assessments of conditions under normal conditions as well as evaluations and assessments under LCAS conditions where additional members may be added using the LCAS ADD state.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: October 20, 2009
    Assignee: Intel Corporation
    Inventors: Soowan Suh, Jing Ling, Juan-Carlos Calderon, Rodrigo Gonzalez
  • Patent number: 7583599
    Abstract: A method and apparatus for transferring data traffic, such as in a SONET/SDH environment, is provided. Two designs are presented, each utilizing a dual device design, where one device performs GFP Framing and the other device performs GFP-T adaptation. The method and apparatus include a first device having a first device FIFO, the first device configured to receive data and assemble data into packets and transfer data across a packet interface when the first device FIFO contains more than N bytes. A second device comprises a second device FIFO, the second device configured to receive data packets from the packet interface and utilize a plurality of thresholds to maintain a quantity of data in the second device FIFO within a predetermined range. Depending on the design employed, control codes, such as 65B_PAD control codes, may be added in the first device under certain conditions to facilitate data transfer.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Jing Ling, Vasan Karighattam, Jean-Michel Caia, Edward Pullin, Mark Feuerstraeter, Juan-Carlos Calderon
  • Patent number: 7564777
    Abstract: In a communication system that uses virtually concatenated payloads, techniques to determine when to declare and when to clear alarm indication signal (AIS) for a group. The declaration of AIS for a group may occur based on when declaration of AIS for a member of a group occurs. The clearing of group AIS may occur based on when clearing of AIS by a last member of a group to clear AIS occurs.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventors: Soowan Suh, Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia
  • Patent number: 7525977
    Abstract: A device for mapping and demapping cells in an orderly manner is provided. The device employs a channel identifier and in certain configurations a buffer and series of stages to provide for relatively ordered, predictable mapping and demapping of data, such as virtual concatenation data.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 28, 2009
    Assignee: Intel Corporation
    Inventors: Eduard Lecha, Vasan Karighattam, Steve J. Clohset, Soowan Suh, Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia
  • Patent number: 7508830
    Abstract: A method and apparatus for determining a read address for received data in a communications network employing virtually concatenated payloads is provided. The method and apparatus comprise determining a minimum write address using a plurality of memory elements and using the minimum write address in connection with received read addresses to determine group read addresses.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: March 24, 2009
    Assignee: Intel Corporation
    Inventors: Soowan Suh, Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Rodrigo Gonzalez
  • Patent number: 7460545
    Abstract: A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: December 2, 2008
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Soowan Suh, Jing Ling, Jean-Michel Caia, Augusto Alcantara, Alejandro Lenero Beracoechea
  • Patent number: 7298744
    Abstract: A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises assigning pseudo indices to payloads having no indices associated therewith and providing both sets of payloads, including indices and pseudo indices, to the single processing path.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: November 20, 2007
    Assignee: Intel Corporation
    Inventors: Soowan Suh, Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia
  • Patent number: 7295564
    Abstract: A method and apparatus for providing a virtual output queue (VoQ) from a received set of data packets in a multi-service system. Each packet is divided into at least one partition, including a last partition that includes packet information, such as error status and packet length. The system receives the packet from a flow, parses the packet into partitions, including a first partition and the last partition, places each last partition into a linked list based on a time when the last partition was received, links the last partition to the first partition, and employs the linked list as the output queue. This system allows for rapid compilation and transmission of different sized packets, and obviates the need for the receiving processor to wait for the last partition to discard a bad packet.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: November 13, 2007
    Assignee: Intel Corporation
    Inventors: Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Anguo T. Huang, Vivek Joshi
  • Patent number: 7154853
    Abstract: A rate policing algorithm for packet flows is based on counters and threshold checking. The rate policing algorithm utilizes a state machine having four links: (1) compliant state to compliant state; (2) transition from compliant state to non-compliant state; (3) non-compliant state to non-compliant state; and (4) transition from non-compliant state to compliant state. Depending on the values obtained from the counters and utilizing the threshold values, it is determined whether a flow rate for packets is compliant or non-compliant.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: December 26, 2006
    Assignee: Intel Corporation
    Inventors: Jean-Michel Caia, Jing Ling, Juan-Carlos Calderon, Vivek Joshi, Anguo T. Huang
  • Publication number: 20060256710
    Abstract: In a communication system that uses virtually concatenated payloads, techniques to determine when to declare and when to clear alarm indication signal (AIS) for a group. The declaration of AIS for a group may occur based on when declaration of AIS for a member of a group occurs. The clearing of group AIS may occur based on when clearing of AIS by a last member of a group to clear AIS occurs.
    Type: Application
    Filed: May 13, 2005
    Publication date: November 16, 2006
    Inventors: Soowan Suh, Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia
  • Publication number: 20060221944
    Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 5, 2006
    Inventors: Jing Ling, Soowan Suh, Juan-Carlos Calderon
  • Patent number: 7065628
    Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Jing Ling, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang
  • Patent number: 7061867
    Abstract: The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: Anguo T. Huang, Jing Ling, Jean-Michel Caia, Juan-Carlos Calderon, Vivek Joshi
  • Patent number: 6944728
    Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 13, 2005
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Jing Ling, Anguo T. Huang
  • Patent number: 6892284
    Abstract: A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: May 10, 2005
    Assignee: Intel Corporation
    Inventors: Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang, Steve J. Clohset
  • Publication number: 20040131055
    Abstract: A method and apparatus for managing multiple pointers is provided. Each pointer may be associated with a partition in a partitioned memory, such as DDR SDRAM used in a high speed networking environment. The system and method include a free pointer pool FIFO, wherein a predetermined quantity of pointers is allocated to the free pointer pool FIFO. The system selects one pointer from the free pointer pool FIFO when writing data to one partition in the partitioned memory, and provides one pointer to the free pointer pool FIFO when reading data from one partition in the partitioned memory. The system and method enable self balancing using the free pointer pool FIFO and decreases the number of memory accesses required. The system can be located on chip.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Jing Ling, Vivek Joshi, Anguo T. Huang
  • Publication number: 20040131069
    Abstract: A method and apparatus for providing a virtual output queue (VoQ) from a received set of data packets in a multi-service system. Each packet is divided into at least one partition, including a last partition that includes packet information, such as error status and packet length. The system receives the packet from a flow, parses the packet into partitions, including a first partition and the last partition, places each last partition into a linked list based on a time when the last partition was received, links the last partition to the first partition, and employs the linked list as the output queue. This system allows for rapid compilation and transmission of different sized packets, and obviates the need for the receiving processor to wait for the last partition to discard a bad packet.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 8, 2004
    Inventors: Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Anguo T. Huang, Vivek Joshi