Patents by Inventor Juan-Carlos Calderon

Juan-Carlos Calderon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040123056
    Abstract: Interleaving memory access includes enabling data included in a receive flow of data to be stored in a first memory bank, enabling data included in a transmit flow of data to be stored in a second memory bank, and alternating access of data in the first memory bank with access of data in the second memory bank.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Jing Ling, Anguo T. Huang
  • Publication number: 20040049650
    Abstract: A memory is divided into a number of partitions. The partitions are grouped into a first group of partitions and a second group of partitions. When required by a port, a partition is assigned to the port from a pool of un-assigned partitions. The pool of un-assigned partitions comprises of un-assigned partitions from the first group of partitions and un-assigned partitions from the second group of partitions. The un-assigned partitions from the first group of partitions are assigned to the port until a first threshold is reached. The un-assigned partitions from the second group of partitions are assigned to the port after the first threshold is reached. A second threshold is used to limit a total number of partitions assigned to the port.
    Type: Application
    Filed: September 11, 2002
    Publication date: March 11, 2004
    Inventors: Jing Ling, Juan-Carlos Calderon, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang, Steve J. Clohset
  • Publication number: 20030225991
    Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Juan-Carlos Calderon, Jing Ling, Jean-Michel Caia, Vivek Joshi, Anguo T. Huang
  • Publication number: 20030223442
    Abstract: Network applications may require a guaranteed rate of throughput, which may be accomplished by using buffer memory reservation to manage a data queue used to store incoming packets. Buffer memory reservation reserves a portion of a data queue as a dedicated queue for each flow, reserves another portion of a data queue as a shared queue, and associates a portion of the shared queue with each flow. The amount of the buffer memory reserved by the dedicated queue sizes and the shared queue portion sizes for all of the flows may exceed the amount of physical memory available to buffer incoming packets.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Anguo T. Huang, Jean-Michel Caia, Jing Ling, Juan-Carlos Calderon, Vivek Joshi
  • Publication number: 20030206522
    Abstract: A rate policing algorithm for packet flows is based on counters and threshold checking. The rate policing algorithm utilizes a state machine having four links: (1) compliant state to compliant state; (2) transition from compliant state to non-compliant state; (3) non-compliant state to non-compliant state; and (4) transition from non-compliant state to compliant state. Depending on the values obtained from the counters and utilizing the threshold values, it is determined whether a flow rate for packets is compliant or non-compliant.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Inventors: Jean-Michel Caia, Jing Ling, Juan-Carlos Calderon, Vivek Joshi, Anguo T. Huang
  • Publication number: 20030185155
    Abstract: The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.
    Type: Application
    Filed: April 2, 2002
    Publication date: October 2, 2003
    Inventors: Anguo T. Huang, Jing Ling, Jean-Michel Caia, Juan-Carlos Calderon, Vivek Joshi
  • Publication number: 20030172178
    Abstract: A system to generate and transfer data frames without frame abortion includes an input source to provide input characters to transmit. A frame writing device generates the data frames having the input characters, stuffed characters, and non-data characters. The frame writing device inserts the stuffed characters into the data frames in place of the input characters that are identical to predetermined special characters utilized in the data frames. No more than two different special characters are utilized in the data frames. A frame transmitting device transmits the data frames. A frame receiving device receives the data frames. A data extraction device extracts the input characters from the data frames. The data extraction device extracts the input characters from the stuffed characters.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Inventors: Eduard Lecha, Juan-Carlos Calderon