Patents by Inventor Juan E. Dominguez

Juan E. Dominguez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817438
    Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: November 14, 2023
    Assignee: Intel Corporationd
    Inventors: Hyoung Il Kim, Bilal Khalaf, Juan E. Dominguez, John G. Meyers
  • Patent number: 11145632
    Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Hyoung Il Kim, Bilal Khalaf, John Gary Meyers
  • Publication number: 20200381406
    Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 3, 2020
    Inventors: Juan E. DOMINGUEZ, Hyoung Il KIM, Bilal KHALAF, John Gary MEYERS
  • Publication number: 20200227393
    Abstract: Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 16, 2020
    Inventors: Hyoung Il KIM, Bilal KHALAF, Juan E. DOMINGUEZ, John G. MEYERS
  • Publication number: 20200075446
    Abstract: Electronic device package technology is disclosed. An electronic device package can comprise a substrate. The electronic device package can also comprise a thermally conductive post extending from the substrate. In addition, the electronic device package can comprise an electronic component supported by the thermally conductive post. The thermally conductive post can facilitate heat transfer between the electronic component and the substrate. Associated systems and methods are also disclosed.
    Type: Application
    Filed: December 31, 2016
    Publication date: March 5, 2020
    Applicant: Intel Corporation
    Inventors: Juan E. Dominguez, Hyoung Il Kim
  • Publication number: 20190229093
    Abstract: Electronic device package technology is disclosed. An electronic device package can comprise a substrate. The electronic device package can also comprise first and second electronic components in a stacked configuration. Each of the first and second electronic components can include an electrical interconnect portion exposed toward the substrate. The electronic device package can further comprise a mold compound encapsulating the first and second electronic components. In addition, the electronic device package can comprise an electrically conductive post extending through the mold compound between the electrical interconnect portion of at least one of the first and second electronic components and the substrate. Associated systems and methods are also disclosed.
    Type: Application
    Filed: October 1, 2016
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: Juan E. Dominguez, Hyoung Il Kim, Mao Guo
  • Publication number: 20180041003
    Abstract: Embodiments herein may relate to a chip-on-chip (CoC) package that includes a first integrated circuit (IC) die with an active side coupled with an active side of a second IC die. The CoC package may further include a substrate with a conductive metal post extending from a side of the substrate. An interposer may be positioned between, and coupled with the conductive metal post and the active side of the first IC die such that an area between an inactive side of the second IC die and the substrate is free of the interposer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: Juan E. Dominguez, Myung Jin Yim
  • Patent number: 8425987
    Abstract: A method including applying an electric charge to a substrate in a chamber; introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including applying a removable electric charge to a substrate; in the presence of the applied electric charge, introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent with an externally applied electric charge.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Harsono S. Simka
  • Patent number: 8344352
    Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
  • Patent number: 8319287
    Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 27, 2012
    Assignee: Intel Corporation
    Inventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy
  • Patent number: 8222746
    Abstract: Noble metal barrier layers are disclosed. In one aspect, an apparatus may include a substrate, a dielectric layer over the substrate, and an interconnect structure within the dielectric layer. The interconnect structure may have a bulk metal and a barrier layer. The barrier layer may be disposed between the bulk metal and the dielectric layer. The barrier layer may include one or more metals selected from iridium, platinum, palladium, rhodium, osmium, gold, silver, rhenium, ruthenium, tungsten, and nickel.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: Adrien R. Lavoie, Juan E. Dominguez, Aaron A. Budrevich
  • Publication number: 20110272811
    Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.
    Type: Application
    Filed: July 18, 2011
    Publication date: November 10, 2011
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
  • Patent number: 7982204
    Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
  • Patent number: 7964174
    Abstract: An apparatus and method for forming catalyst particles to grow nanotubes is disclosed. In addition, an apparatus and method for forming nanotubes using the catalytic particles is also disclosed. The particles formed may have different diameters depending upon how they are formed. Once formed, the particles are deposited on a substrate. Once deposited, the mobility of the particles is restricted and nanotubes and/or nanotube portions are grown on the particles. Nanotube portions having different diameters may be formed and the portions may be connected to form nanotubes with different diameters along the length of the nanotube.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: June 21, 2011
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Juan E. Dominguez, Chin-Chang Cheng
  • Patent number: 7964746
    Abstract: Copper precursors useful for depositing copper or copper-containing films on substrates, e.g., microelectronic device substrates or other surfaces. The precursors includes copper compounds of various classes, including copper borohydrides, copper compounds with cyclopentadienyl-type ligands, copper compounds with cyclopentadienyl-type and isocyanide ligands, and stabilized copper hydrides. The precursors can be utilized in solid or liquid forms that are volatilized to form precursor vapor for contacting with the substrate, to form deposited copper by techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or rapid vapor deposition (digital CVD).
    Type: Grant
    Filed: March 30, 2008
    Date of Patent: June 21, 2011
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Tianniu Chen, Chongying Xu, Thomas H. Baum, Bryan C. Hendrix, Jeffrey F. Roeder, Juan E. Dominguez, Adrien R. Lavoie, Harsono S. Simka
  • Patent number: 7858525
    Abstract: A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka, Bryan C. Hendrix, Gregory T. Stauf
  • Publication number: 20100230817
    Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.
    Type: Application
    Filed: May 27, 2010
    Publication date: September 16, 2010
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
  • Patent number: 7749906
    Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
  • Publication number: 20100166981
    Abstract: A method including applying an electric charge to a substrate in a chamber; introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including applying a removable electric charge to a substrate; in the presence of the applied electric charge, introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent. A method including introducing an organometallic substituent into the chamber, the organometallic substituent including a metal ligand and an organic ligand; and depositing a metal film by reducing the metal ligand of the organometallic substituent with an externally applied electric charge.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: JUAN E. DOMINGUEZ, ADRIEN R. LAVOIE, JOHN J. PLOMBON, HARSONO S. SIMKA
  • Publication number: 20100140717
    Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 10, 2010
    Inventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy