Patents by Inventor Juan E. Dominguez
Juan E. Dominguez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7704895Abstract: A method for depositing a high-k dielectric material on a semiconductor substrate is disclosed. The method includes applying a chemical bath to a surface of a substrate, rinsing the surface, applying a co-reactant bath to the surface of the substrate, and rinsing the surface. The chemical bath includes a metal precursor which includes at least a hafnium compound, an aluminium compound, a titanium compound, zirconium compound, a scandium compound, a yttrium compound or a lanthanide compound.Type: GrantFiled: April 2, 2008Date of Patent: April 27, 2010Assignee: Intel CorporationInventors: Adrien R. Lavoie, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Mansour Moinpour
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Publication number: 20100098960Abstract: A magnetic insulator nanolaminate device comprises a metal magnetic layer formed on a substrate, an insulating layer formed on the metal magnetic layer, wherein the insulating layer is formed by nitriding a portion of the metal magnetic layer, a chelating group layer formed on the insulating layer, and a metal seed layer bonded to the chelating group layer. The magnetic insulator nanolaminate device may be formed by depositing a metal layer on a substrate, converting a portion of the metal layer into an insulating layer using a nitridation process, and depositing a metal seed layer onto the insulating layer using a metal immobilization process, wherein the metal seed layer enables the deposition of a metal layer onto the insulating layer.Type: ApplicationFiled: June 18, 2007Publication date: April 22, 2010Inventors: Juan E. Dominguez, Arnel M. Fajardo, Adrien R. Lavoie
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Patent number: 7687225Abstract: Systems and techniques involving optical coatings for semiconductor devices. An implementation includes a substantially isotropic, heterogeneous anti-reflective coating having a substantially equal thickness normal to any portion of a substrate independent of the orientation of the portion.Type: GrantFiled: September 29, 2004Date of Patent: March 30, 2010Assignee: Intel CorporationInventors: Sergei V. Koveshnikov, Juan E. Dominguez, Kyle Y. Flanigan, Ernisse Putna
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Patent number: 7687911Abstract: A method for forming a silicon alloy based barrier layer comprises providing a substrate having a dielectric layer including a trench, placing the substrate in a reactor, and carrying out a process cycle, wherein the process cycle comprises introducing a silicon containing precursor into the reactor, introducing a metal containing precursor into the reactor, and introducing a co-reactant into the reactor, wherein the silicon, metal, and co-reactant react to form a silicon alloy layer that is conformally deposited on a bottom and a sidewall of the trench.Type: GrantFiled: September 7, 2006Date of Patent: March 30, 2010Assignee: Intel CorporationInventors: Juan E. Dominguez, Adrien R. Lavoie
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Patent number: 7682891Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.Type: GrantFiled: December 28, 2006Date of Patent: March 23, 2010Assignee: Intel CorporationInventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy
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Publication number: 20100022083Abstract: A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.Type: ApplicationFiled: August 27, 2009Publication date: January 28, 2010Applicant: INTEL CORPORATIONInventors: Florian Gstrein, Valery M. Dubin, Juan E. Dominguez, Adrien R. Lavoie
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Patent number: 7635503Abstract: Embodiments of the present invention provide methods for the fabrication of carbon nanotubes using composite metal films. A composite metal film is fabricated to provide uniform catalytic sites to facilitate the uniform growth of carbon nanotubes. Further embodiments provide embedded nanoparticles for carbon nanotube fabrication. Embodiments of the invention are capable of maintaining the integrity of the catalytic sites at temperatures used in carbon nanotube fabrication processes, 600 to 1100° C.Type: GrantFiled: February 21, 2006Date of Patent: December 22, 2009Assignee: Intel CorporationInventors: Juan E. Dominguez, Valery M. Dubin, Florian Gstrein, Michael Goldstein
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Patent number: 7625817Abstract: A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.Type: GrantFiled: December 30, 2005Date of Patent: December 1, 2009Assignee: Intel CorporationInventors: Florian Gstrein, Valery M. Dubin, Juan E. Dominguez, Adrien R. Lavoie
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Publication number: 20090253270Abstract: A method for depositing a high-k dielectric material on a semiconductor substrate is disclosed. The method includes applying a chemical bath to a surface of a substrate, rinsing the surface, applying a co-reactant bath to the surface of the substrate, and rinsing the surface. The chemical bath includes a metal precursor which includes at least a hafnium compound, an aluminium compound, a titanium compound, zirconium compound, a scandium compound, a yttrium compound or a lanthanide compound.Type: ApplicationFiled: April 2, 2008Publication date: October 8, 2009Inventors: Adrien R. Lavoie, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Mansour Moinpour
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Publication number: 20090209777Abstract: This invention relates to organometallic compounds having the formula (L1)M(L2)y wherein M is a metal or metalloid, L1 is a substituted or unsubstituted anionic 6 electron donor ligand, L2 is the same or different and is (i) a substituted or unsubstituted anionic 2 electron donor ligand, (ii) a substituted or unsubstituted anionic 4 electron donor ligand, (iii) a substituted or unsubstituted neutral 2 electron donor ligand, or (iv) a substituted or unsubstituted anionic 4 electron donor ligand with a pendant neutral 2 electron donor moiety; and y is an integer of from 1 to 3; and wherein the sum of the oxidation number of M and the electric charges of L1 and L2 is equal to 0; a process for producing the organometallic compounds, and a method for producing a film or coating from the organometallic compounds. The organometallic compounds are useful in semiconductor applications as chemical vapor or atomic layer deposition precursors for film depositions.Type: ApplicationFiled: January 12, 2009Publication date: August 20, 2009Inventors: David M. Thompson, Joan Geary, Adrien R. Lavoie, Juan E. Dominguez
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Publication number: 20090200524Abstract: This invention relates to organometallic compounds having the formula L1ML2 wherein M is a metal or metalloid, L1 is a substituted or unsubstituted 6 electron donor anionic ligand, and L2 is a substituted or unsubstituted 6 electron donor anionic ligand, wherein L1 and L2 are the same or different, a process for producing the organometallic compounds, and a method for producing a film or coating from the organometallic compounds. The organometallic compounds are useful in semiconductor applications as chemical vapor or atomic layer deposition precursors for film depositions.Type: ApplicationFiled: January 12, 2009Publication date: August 13, 2009Inventors: David M. Thompson, Joan Geary, Adrien R. Lavoie, Juan E. Dominguez
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Patent number: 7550385Abstract: A method for forming a metal carbide layer begins with providing a substrate, an organometallic precursor material, at least one doping agent such as nitrogen, and a plasma such as a hydrogen plasma. The substrate is placed within a reaction chamber; and heated. A process cycle is then performed, where the process cycle includes pulsing the organometallic precursor material into the reaction chamber, pulsing the doping agent into the reaction chamber, and pulsing the plasma into the reaction chamber, such that the organometallic precursor material, the doping agent, and the plasma react at the surface of the substrate to form a metal carbide layer. The process cycles can be repeated and varied to form a graded metal carbide layer.Type: GrantFiled: September 30, 2005Date of Patent: June 23, 2009Assignee: Intel CorporationInventors: Adrien R. Lavoie, Valery M. Dubin, Juan E. Dominguez, Kevin P. O'Brien, Steven W. Johnston, John D. Peck, David M. Thompson, David W. Peters
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Patent number: 7507521Abstract: An optically tuned SLAM (Sacrificial Light-Absorbing Material) may be used in a via-first dual damascene patterning process to facilitate removal of the SLAM. The monomers used to produce the optically tuned SLAM may be modified to place an optically sensitive structure in the backbone of the SLAM polymer. The wafer may be exposed to a wavelength to which the SLAM is tuned prior to etching and/or ashing steps to degrade the optically tuned SLAM and facilitate removal.Type: GrantFiled: August 9, 2004Date of Patent: March 24, 2009Assignee: Intel CorporationInventors: Kyle Y. Flanigan, Juan E. Dominguez, Sergei V. Koveshnikov, Ernisse Putna
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Publication number: 20090022958Abstract: A method for fabricating an amorphous metal-metalloid alloy layer for use in an IC device comprises providing a substrate in a reactor that includes a dielectric layer having a trench, pulsing a metal precursor into the reactor to deposit within the trench, wherein the metal precursor is selected from the group consisting of CpTa(CO)4, PDMAT, TBTDET, TaCl5, Cp2Co, Co-amidinates, Cp2Ru, Ru-diketonates, and Ru(CO)4, purging the reactor after the metal precursor pulse, pulsing a metalloid precursor into the reactor to react with the metal precursor and form an amorphous metal-metalloid alloy layer, wherein the metalloid precursor is selected from the group consisting of BH3, BCl3, catechol borane, AlMe3, methylpyrrolidinealane, AICl3, SiH4, SiH2Cl2, SiCl4, tetraalkylsilanes, GeH4, GeH2Cl2, GeCl4, SnCl4, trialkylantimony, SbMe3, SbEt3, arsine, and trimethylarsine, purging the reactor after the metalloid precursor pulse, and annealing the amorphous metal-metalloid layer at a temperature between 50° C. and 700° C.Type: ApplicationFiled: July 19, 2007Publication date: January 22, 2009Inventors: John J. Plombon, Harsono S. Simka, Adrien R. Lavoie, Juan E. Dominguez
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Patent number: 7476615Abstract: An iodine-doped ruthenium barrier layer for use with copper interconnects within integrated circuits is formed using novel, iodine-containing ruthenium precursors in an ALD or CVD process. Ruthenium precursors that may be used include ruthenium containing carbonyls, arenes, cyclopentadienyls, and certain other ruthenium containing compounds. The ruthenium precursors include iodine to catalyze a subsequent copper metal deposition and to smooth the surface of the ruthenium layer. The iodine concentration across the thickness of the ruthenium barrier layer may be constant or may be graded.Type: GrantFiled: November 1, 2006Date of Patent: January 13, 2009Assignee: Intel CorporationInventors: Joseph H. Han, Harsono S. Simka, Adrien R. Lavoie, Juan E. Dominguez, John J. Plombon
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Publication number: 20080311400Abstract: An apparatus and method for forming catalyst particles to grow nanotubes is disclosed. In addition, an apparatus and method for forming nanotubes using the catalytic particles is also disclosed. The particles formed may have different diameters depending upon how they are formed. Once formed, the particles are deposited on a substrate. Once deposited, the mobility of the particles is restricted and nanotubes and/or nanotube portions are grown on the particles. Nanotube portions having different diameters may be formed and the portions may be connected to form nanotubes with different diameters along the length of the nanotube.Type: ApplicationFiled: August 25, 2008Publication date: December 18, 2008Inventors: Valery M. Dubin, Juan E. Dominguez, Chin-Chang Cheng
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Patent number: 7459392Abstract: A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.Type: GrantFiled: March 31, 2005Date of Patent: December 2, 2008Assignee: Intel CorporationInventors: Steven W. Johnston, Juan E. Dominguez, Michael L. McSwiney
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Patent number: 7435679Abstract: Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.Type: GrantFiled: December 7, 2004Date of Patent: October 14, 2008Assignee: Intel CorporationInventors: Steven W. Johnston, Juan E. Dominguez
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Publication number: 20080242880Abstract: Copper precursors useful for depositing copper or copper-containing films on substrates, e.g., microelectronic device substrates or other surfaces. The precursors includes copper compounds of various classes, including copper borohydrides, copper compounds with cyclopentadienyl-type ligands, copper compounds with cyclopentadienyl-type and isocyanide ligands, and stabilized copper hydrides. The precursors can be utilized in solid or liquid forms that are volatilized to form precursor vapor for contacting with the substrate, to form deposited copper by techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or rapid vapor deposition (digital CVD).Type: ApplicationFiled: March 30, 2008Publication date: October 2, 2008Inventors: Tianniu Chen, Chongying Xu, Thomas H. Baum, Bryan C. Hendrix, Jeffrey F. Roeder, Juan E. Dominguez, Adrien R. Lavoie, Harsono S. Simka
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Publication number: 20080237861Abstract: A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition process. A method including forming an opening through a dielectric layer to a contact point; introducing a fluorine-free copper film precursor and a co-reactant; and forming a copper-containing seed layer in the opening. A system including a computer including a microprocessor electrically coupled to a printed circuit board, the microprocessor including conductive interconnect structures formed from fluorine-free organometallic precursor.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Inventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka, Bryan C. Hendrix, Gregory T. Stauf