Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

Abstract: An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.

Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes a core, a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory, and a stall circuit coupled to the core configured to stall or resume the core in response to one or more inputs.

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.

Abstract: An apparatus relating generally to generation of a compressed matrix is disclosed. In this apparatus, a row determination block is coupled to receive input samples and configuration information and is configured to provide a row output for each of the input samples. A matrix determination block is coupled to receive the row output and the configuration information. The matrix determination block is configured to: generate pivot row indices responsive to the configuration information; generate each outer product using the row output and any of the pivot row indices therefor; and accumulate, for each of the input samples, the outer product therefor for inclusion in the compressed matrix.

Abstract: An embodiment of the present invention provides for the ad-hoc configuration of femtocells using spectrum sensing for the selection of spectrum channels. One or more embodiments of the invention determine frequency bands that are not reserved by macrocells in a location, and perform spectrum sensing to determine communication channels in unreserved frequency bands that are being used by other femtocells in range. In this manner, femtocells can be deployed and configured in an ad-hoc manner without external coordination or control between deployed femtocells.

Abstract: In one embodiment, an integrated circuit for providing distributed temperature sensing is disclosed. For example, the integrated circuit comprises a plurality of circuit components, an internal temperature sensing device deployed among the plurality of circuit components; and a plurality of ring-oscillators deployed among the plurality of circuit components, wherein at least one of the plurality of ring-oscillators is deployed adjacent to the internal temperature sensing device, where the plurality of ring-oscillators is used to provide one or more temperature measurements, e.g., a temperature gradient, for the integrated circuit.

Abstract: A method of reducing startup time of an embedded system can include: instantiating a circuit, specified by a first circuit design, within an integrated circuit (IC), booting a first build of an operating system executed by a processor to a steady state, and responsive to achieving the steady state, storing a circuit operational state of the circuit instantiated within the IC, an operational state of the processor, and a state of an executable memory utilized by the processor. A second circuit design can be created and a second build of the operating system can be created that collectively specify the circuit operational state, the operational state of the processor, and a state of an executable memory. The second circuit design and the second build of the operating system can be stored in the memory.

Abstract: A method of operating an integrated circuit having a circuit block configurable by a configuration memory is disclosed. The method includes determining whether to operate the circuit block in a normal operation mode or a low power mode. The configuration memory is loaded with normal operation mode configuration data for the circuit block if the normal operation mode is determined. If the low power mode is determined, the configuration memory is loaded with low power mode configuration data for the circuit block.

Abstract: An embodiment of the present invention provides for the ad-hoc configuration of femtocells using spectrum sensing for the selection of spectrum channels. One or more embodiments of the invention determine frequency bands that are not reserved by macrocells in a location, and perform spectrum sensing to determine communication channels in unreserved frequency bands that are being used by other femtocells in range. In this manner, femtocells can be deployed and configured in an ad-hoc manner without external coordination or control between deployed femtocells.

Abstract: A programmable integrated circuit performs an initial partial configuration of the programmable integrated circuit in response to receiving an activation signal. In this way, the programmable integrated circuit enables an initial functionality of the programmable integrated circuit. The programmable integrated circuit then performs a subsequent partial configuration of the programmable integrated circuit for enabling additional functionality of the programmable integrated circuit. In some embodiments, the programmable integrated circuit receives an input signal indicating a stimulus in an environment of the programmable integrated circuit and determines based on the input signal whether to perform the subsequent partial configuration of the programmable integrated circuit or generate a power down signal for powering down the programmable integrated circuit without performing the subsequent partial configuration.