Patents by Inventor Juan-Jann Jou

Juan-Jann Jou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060194426
    Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 31, 2006
    Inventors: Chin-Tien Yang, Juan-Jann Jou, Yu-Hua Lee, Chia-Hung Lai
  • Patent number: 7056821
    Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: June 6, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Tien Yang, Juan-Jann Jou, Yu-Hua Lee, Chia-Hung Lai
  • Publication number: 20060040498
    Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
    Type: Application
    Filed: August 17, 2004
    Publication date: February 23, 2006
    Inventors: Chin-Tien Yang, Juan-Jann Jou, Yu-Hua Lee, Chia-Hung Lai
  • Publication number: 20050173799
    Abstract: A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 11, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Juan-Jann Jou, Yu-Hua Lee, Chin-Tien Yang, Chia-Hung Lai, Connie Hsu, Mu-Yi Lin, Min Cao, Chia-Yu Ku, Yuh-Da Fan