Method for manufacturing dual damascene structure with a trench formed first
A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
This application is a division of U.S. patent application Ser. No. 10/919,328, filed Aug. 17, 2004.
The present invention relates to a method of manufacturing a dual damascene structure, and more particularly, to a method of manufacturing a dual damascene structure with a trench formed first.
BACKGROUND OF THE INVENTIONThe manufacture of integrated circuits (ICs) usually adopts multilevel interconnects to build up 3-D interconnection structures in highly dense devices, as IC device performance extends to higher levels. In devices, the metal lines of the first layer are generally electrically coupled to the drains/sources of devices through vias, and the interconnects between the devices are coupled by the metal lines of other layers. On the other hand, the multilevel interconnects between the metal lines are separated by inter-metal dielectric (IMD) layers, while the respective metal layers are connected by via plugs. The dual damascene process is currently developed for forming via plugs and metal interconnects at the same time.
As to the metals, copper is gradually being substituted for aluminum, because copper comprises the properties of a high melting point and a low resistance (about 1.7 μΩ-cm), and is more capable of preventing electro-migration. However, copper itself is inclined to oxidize and tends to react with other materials at low temperatures. Further, no effective dry etching process exists for copper. Nevertheless, these issues are overcome by improved diffusion barrier materials and progressive processes, such as damascene process, and chemical mechanical polishing (CMP).
The via 116 is formed by etching the second etching stop layer 111, the inter-metal dielectric layer 109, and the first etching stop layer 107, as illustrated in
In turn, the sacrificial layer 115 is etched back, and a photoresist layer 117 is next coated thereon, as shown in
According to the aforementioned description, the conventional method for manufacturing dual damascene is to form a trench following a via. This method, however, conceals some problems. As mentioned above, the metal layer 103 has been exposed to air before the sacrificial layer 115 is filled therein. Using copper as the metal layer dramatically affects the quality of the devices, since copper is inclined to oxidize. Therefore the queue time (Q-time) should be controlled precisely.
Moreover, micro trenches 203 and fences 201 issues commonly occur in the conventional process, as shown in
In addition, the dielectric layer 109 is generally constituted by porous low-k materials, through which residual NH-group components in the substrate readily pass to neutralize with the photoresist layer, and consequently react to be photoresist scum. Therefore the photoresist is not developed and patterned well, which also leads to a decrease in the production yield.
SUMMARY OF THE INVENTIONOne of the objectives of the present invention is to provide a method for manufacturing a dual damascene structure with a trench formed first, in order to reduce Q-time when copper is exposed to the air and also to simplify the process by omitting a post-baking step following etching a via.
Another objective of the present invention is to improve the surface quality of the photoresist layer for etching a via by planarizing the sacrificial layer. The photolithography process thus has a wider control window.
Yet another objective of the present invention is to provide a method for manufacturing a dual damascene structure with a trench formed first. No photoresist scum issue is caused by neutralization of the photoresist with NH— group components due to the greater open area of the trench. The photoresist is therefore patterned and transferred more clearly and more precisely.
Yet another objective of the present invention is to provide a method for reducing micro trenches and fences by means of a sacrificial layer with substantially the same etching rate selectivity as an inter-metal dielectric layer; both of which and the photoresist are consequently easily stripped by a wet or dry cleaning process or by a wet or dry etching process.
According to the aforementioned objectives of the present invention, a method for manufacturing a dual damascene structure with a trench formed first is provided. The method of manufacture has the following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, a second etching stop layer, and a first patterned photoresist layer are subsequently formed thereon. The first patterned photoresist layer is used as a mask, and a trench is then formed by etching through the second etching stop layer and stopping in the dielectric layer at a predetermined depth. The trench is filled with a sacrificial layer thereafter and is next planarized. Then a second patterned photoresist layer is formed thereon as a mask for etching a via. The second patterned photoresist layer and the sacrificial layer are then both removed. The first etching stop layer is next etched through to expose the first metal layer. A second metal layer is subsequently filled therein and is also planarized.
The first metal layer and the second metal layer discussed above comprise copper, while the dielectric layer comprises fluorinated silicate glass (FSG), silicon dioxide, black diamond (BD), SiLK, CORAL, methyl silsesquioxane (MSQ), or hydrogen silsesquioxane (HSQ), of which the dielectric constant is preferably from about 1.0 to about 4.0.
The predetermined depth of the trench discussed above is preferably less than the thickness of the dielectric layer, yet the sacrificial layer is 0.5-1.5 times the thickness of the dielectric layer. The etching rate ratio of the sacrificial layer to the dielectric layer, moreover, is around 0.7:1 to 1.3:1. On the other hand, the second patterned photoresist layer and the dielectric layer are separated by the sacrificial layer and the second etching stop layer to prevent the photoresist layer from contacting NH— group components. Additionally, the photoresist layer is positioned on the sacrificial layer that has been planarized, so the photoresist layer is more capable of being patterned and transferred.
The method for manufacturing a dual damascene structure with a trench formed first in accordance with the present invention not only reduces the Q-time when copper is exposed to the air, but also eliminates one step of baking, by which the process is effectively simplified. Furthermore, the problems of micro trenches and fences, as well as the issue of neutralization of the photoresist layer with the NH— group components are successfully solved; as a result, the control window of the photolithography process is increased.
BRIEF DESCRIPTION OF THE DRAWINGSThe foregoing aspects and many of the attendant advantages of this invention will become more apparent by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
A method for manufacturing a dual damascene structure with a trench formed first is disclosed in the invention, in order to reduce Q-time when copper is exposed to the air to shorten the process, to increase development ability of the photoresist to increase the control windows of the photolithography process, and also to eliminate the problems of micro trenches and fences. As a result, the productivity and the yield of semiconductor devices are effectively improved in accordance with the invention. The making and using of the preferred embodiment of the present invention are discussed in detail below with reference to drawings. It should be appreciated, however, those skilled in the art would make and use in a wide variety ways of the present invention without departing from the spirit and the scope of the invention.
Referring to
The sacrificial layer 311 is next planarized to the thickness of the second etching stop layer 303, as shown in
Referring to
The first etching stop layer 307 is subsequently etched through to expose the first metal layer 302. Referring to
A third etching stop layer 317 is next formed on the metal layer 315 for subsequent processes, as illustrated in
According to the aforementioned preferred embodiment of the present invention, a method of manufacturing a dual damascene structure with a trench formed first is provided, which effectively improves the conventional art. For example, the micro trenches and the fences during the conventional process are eliminated by use of the proper sacrificial materials. The control windows of the photolithography process are increased by the step of planarizing the sacrificial materials. In addition, the photoresist scum is removed effectively due to the greater open area of the trench. On the other hand, the Q-time when the metal is exposed to the air is reduced, and the metal is consequently protected from oxidation, which is especially beneficial to copper processes. A post-baking step is further omitted in accordance with the present invention; hence the process is simplified.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, these are, of course, merely examples to help clarify the invention and are not intended to limit the invention. It will be understood by those skilled in the art that various changes, modifications, and alterations in forms and details may be made therein without departing from the spirit and scope of the invention, as set forth in the following claims.
Claims
1. A method of manufacturing a dual damascene structure with a trench formed first, comprising the steps of:
- forming a dielectric layer on a substrate;
- patterning the dielectric layer to form a trench on an upper part of the dielectric layer;
- filling with a sacrificial layer into the trench;
- patterning the sacrificial layer and the dielectric layer to form a via on a lower part of the dielectric layer;
- removing the sacrificial layer;
- filling with a metal layer; and
- planarizing the metal layer.
2. The method of claim 1, wherein the dielectric layer further comprises a first etching stop layer below the dielectric layer, and a second etching stop layer above the dielectric layer.
3. The method of claim 2, wherein the step of patterning the dielectric layer to form the trench on the upper part of the dielectric layer, further comprising:
- forming a first patterned photoresist layer on the second etching stop layer; and
- etching through the second etching stop layer and stopping in the dielectric layer.
4. The method of claim 2, wherein the step of patterning the sacrificial layer and the dielectric layer to form the via on the lower part of the dielectric layer is terminated at the first etching stop layer.
5. The method of claim 2, wherein the first etching stop layer comprises a diffusion-barrier layer.
6. The method of claim 2, wherein the second etching stop layer comprises a hard mask layer.
7. The method of claim 2, wherein the second etching stop layer comprises an anti-reflection layer.
8. The method of claim 1, further comprising a step of planarizing the sacrificial layer prior to the step of patterning the sacrificial layer and the dielectric layer to form the via on the lower part of the dielectric layer.
9. The method of claim 1, wherein the metal layer comprises copper.
10. The method of claim 1, wherein the dielectric layer is made of a material selected from a group consisting of fluorinated silicate glass (FSG), silicon dioxide, black diamond (BD), SiLK, CORAL, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (HSQ).
11. The method of claim 1, wherein the dielectric layer has a dielectric constant of about 1.0 to about 4.0.
12. The method of claim 1, wherein a depth of the trench is less than a thickness of the dielectric layer.
13. The method of claim 1, wherein the sacrificial layer is 0.5-1.5 times a thickness of the dielectric layer.
14. The method of claim 1, wherein an etching rate ratio of the sacrificial layer to the dielectric layer is about 0.7:1 to 1.3:1.
15. A dual damascene process, comprising the steps of:
- forming a dielectric layer on a substrate, wherein an upper portion of the dielectric layer comprises a sacrificial layer;
- removing a partial portion of the sacrificial layer and a partial portion of the dielectric layer, wherein the partial portion of the dielectric layer is directly under the partial portion of the sacrificial layer;
- removing the sacrificial layer to form a dual damascene structure; and
- filling with a metal layer.
16. The dual damascene process of claim 15, wherein the dielectric layer further comprises a first etching stop layer below the dielectric layer, and a second etching stop layer above the dielectric layer.
17. The dual damascene process of claim 16, wherein the step of removing a partial portion of the sacrificial layer and a partial portion of the dielectric layer is terminated at the first etching stop layer.
18. The dual damascene process of claim 16, wherein the first etching stop layer comprises a diffusion-barrier layer.
19. The dual damascene process of claim 16, wherein the second etching stop layer comprises a hard mask layer, or an anti-reflection layer.
20. The dual damascene process of claim 15, wherein the metal layer comprises copper.
21. The dual damascene process of claim 15, wherein the dielectric layer is made of a material selected from a group consisting of fluorinated silicate glass (FSG), silicon dioxide, black diamond (BD), SiLK, CORAL, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (HSQ).
22. The dual damascene process of claim 15, wherein the dielectric layer has a dielectric constant of about 1.0 to about 4.0.
23. The dual damascene process of claim 15, wherein a depth of the trench is less than a thickness of the dielectric layer.
24. The dual damascene process of claim 15, wherein the sacrificial layer is 0.5-1.5 times a thickness of the dielectric layer.
25. The dual damascene process of claim 15, wherein an etching rate ratio of the sacrificial layer to the dielectric layer is about 0.7:1 to 1.3:1.
Type: Application
Filed: Apr 11, 2006
Publication Date: Aug 31, 2006
Inventors: Chin-Tien Yang (Hsinchu), Juan-Jann Jou (Tainan Hsien), Yu-Hua Lee (Hsinchu), Chia-Hung Lai (Hsinchu)
Application Number: 11/401,308
International Classification: H01L 21/4763 (20060101);