Patents by Inventor Juan Yuan

Juan Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266097
    Abstract: Image analysis methods based on an ultrasound imaging device and ultrasound imaging devices are provided. An image analysis method may include: obtaining an image of a first section of a target object; generating a first analysis result corresponding to the target object according to the image of the first section; obtaining an image of a second section of the target object; generating a second analysis result corresponding to the target object according to the image of the second section; generating a diagnostic analysis result of the target object according to the first analysis result and the second analysis result; and displaying the diagnostic analysis result of the target object.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: April 1, 2025
    Assignees: Shenzhen Mindray Bio-Medical Electronics Co., Ltd., Shenzhen Mindray Scientific Co., Ltd.
    Inventors: Xuehao Gong, Shuo Liu, Lei Zhu, Zhijie Chen, Juan Yuan
  • Publication number: 20210090254
    Abstract: Image analysis methods based on an ultrasound imaging device and ultrasound imaging devices are provided. An image analysis method may include: obtaining an image of a first section of a target object; generating a first analysis result corresponding to the target object according to the image of the first section; obtaining an image of a second section of the target object; generating a second analysis result corresponding to the target object according to the image of the second section; generating a diagnostic analysis result of the target object according to the first analysis result and the second analysis result; and displaying the diagnostic analysis result of the target object.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Inventors: Xuehao Gong, Shuo Liu, Lei Zhu, Zhijie Chen, Juan Yuan
  • Patent number: 8062536
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: November 22, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Publication number: 20100173490
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Application
    Filed: March 22, 2010
    Publication date: July 8, 2010
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Patent number: 7718079
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: May 18, 2010
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Patent number: 7284862
    Abstract: The present invention contemplates to employ an eye-tracking device in an ophthalmic adaptive-optics system such that slow wavefront sensor and aberration-compensating element can be sufficient for the application. The present invention further contemplates to implement with the eye-tracking device a motion-compensating mechanism into the system such that the pupil images on both the wavefront sensor and the aberration-compensating element remain stationary during the operation of the system.
    Type: Grant
    Filed: November 13, 2004
    Date of Patent: October 23, 2007
    Assignee: MD Lasers & Instruments, Inc.
    Inventors: Ming Lai, Mei Juan Yuan
  • Patent number: 7271101
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: September 18, 2007
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Patent number: 7078346
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: July 18, 2006
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen-Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Patent number: 7037802
    Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: May 2, 2006
    Assignee: United Microelectronics Corporation
    Inventors: Ming-Sheng Yang, Juan-Yuan Wu, Water Lur
  • Patent number: 7018906
    Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: March 28, 2006
    Assignee: United Microelectronics Corporation
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Patent number: 7001713
    Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: February 21, 2006
    Assignee: United Microelectronics, Corp.
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Publication number: 20060009005
    Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relatively small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask has an opening at a central part of each relatively large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.
    Type: Application
    Filed: November 9, 2004
    Publication date: January 12, 2006
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Patent number: 6952435
    Abstract: The present invention contemplates a method and apparatus to generate a laser probe beam free of speckles. The present invention employs a holographic phase plate inserted in a laser beam path to modulate the relative phase across the beam. The holographic phase plate is designed to optimize the phase modulation across the beam while to minimize the degradation of the beam quality. The modulated laser beam has only a small and confined divergent angle and can then be refocused or collimated into a narrow and near collimated probe beam. The present invention further rotates the holographic phase plate to randomize the speckles in a time sequence. As a result, the probe beam preserves substantially the beam quality of a laser and produces substantially no speckles on image of its, intersection with a surface or material.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: October 4, 2005
    Inventors: Ming Lai, Mei Juan Yuan
  • Patent number: 6854847
    Abstract: The optical tracking device of the present invention is contemplated to obtain a large tracking range in an open loop configuration. The tracking device projects and scans two probe beams across a symmetric reference landmark that has at least two symmetric lines or axes. The two probe beams scan repeatedly and alternatively along two directions of which each is perpendicular to a symmetric line of the reference mark. For each scan, a substantially symmetric profile is generated in the scattered light as the beam scans across the boundary on each side of the symmetric reference. This symmetric profile in the scattered light is detected and used to determine the position of the related symmetric line. The position detection of the symmetric line is independent from the object's movement along the direction of the symmetric line. The scattered-light signal from the two probe beams is separated by synchronized detection in the time domain.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: February 15, 2005
    Inventors: Ming Lai, Mei Juan Yuan
  • Publication number: 20050032328
    Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.
    Type: Application
    Filed: September 13, 2004
    Publication date: February 10, 2005
    Inventors: Ming-Sheng Yang, Juan-Yuan Wu, Water Lur
  • Patent number: 6838357
    Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed A number of shallow trenches are formed between the active regions An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed The oxide layer is planarized to expose the silicon nitride layer.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: January 4, 2005
    Assignee: United Microelectronics Corporation
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Patent number: 6809022
    Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: October 26, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Juan-Yuan Wu, Water Lur
  • Patent number: 6810511
    Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: October 26, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
  • Patent number: 6790742
    Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: September 14, 2004
    Assignee: United Microelectronics Corporation
    Inventors: Ming-Sheng Yang, Juan-Yuan Wu, Water Lur
  • Publication number: 20030185999
    Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
    Type: Application
    Filed: March 25, 2003
    Publication date: October 2, 2003
    Inventors: Chih-Chien Liu, Juan-Yuan Wu, Water Lur