Abstract: A method for forming a gate on a substrate for manufacturing semiconductor devices is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and then, a amorphous silicon layer is formed thereon. The stack of amorphous and polysilicon layers is defined to form a gate structure on gate oxide layer. Next, a thermal treatment is performed on the gate structure.

Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.

Abstract: The present invention relates to a method for forming excellent conformity due to improved surface sensitivity. A substrate is providing on which a transistor is formed. Moreover, a blanket first dielectric layer is deposited over the substrate. Then, a first photoresist layer is formed over the dielectric layer, wherein the first photoresist layer is defined and etched to form a contact opening. Further, a first conductive layer is formed to fill the contact opening, and performing an etching process to remove the first conductive layer to form a node contact. Consequentially, a second conductive layer is deposited over the first dielectric layer and the node contact. A second photoresist layer is formed over the second conductive layer, wherein the second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor. Next, a hemispherical silicon grain (HSG) is formed over and on a sidewall of the second conductive layer.

Abstract: A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide layer. While forming the second oxide layer a triangular or trapezium profile is formed due to an etching effect to the corner. An argon flow with a low speed of etching/deposition is provided to form a third oxide layer. The gap filling is completed.

Abstract: A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

Abstract: A method of forming a DRAM capacitor. A hemispherical grain structure is formed on the surface of the bottom electrode of the capacitor. By employing an additional annealing under a dopant contained ambient, the dopant is diffused into the hemispherical grain structure and distributed at the surface area of the hemispherical grain region.

Abstract: A method of designing an active region pattern with a shifted dummy pattern, wherein an integrated circuit having an original active region pattern thereon is provided. The original active region pattern is expanded with a first parameter of line width to obtain a first pattern. By subtracting the first pattern, a second pattern is obtained. A dummy pattern which comprises an array of a plurality of elements is provided. By shifting the elements, a shifted dummy pattern is obtained. The second pattern and the shifted dummy pattern are combined, so that an overlapped region thereof is extracted as a combined dummy pattern. The combined dummy pattern is expanded with a second parameter of line width, so that a resultant dummy pattern is obtained. The resultant dummy pattern is added to the first pattern, so that the active region pattern with a shifted dummy pattern is obtained.

Abstract: A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the substrate; second, form a copper phosphide layer on the copper layer; and finally, form a silicon nitride layer on the copper phosphide layer. Herein, the copper phosphide layer is formed by a plasma enhanced chemical vapor deposition process. Therefore, any copper oxide layer that covers copper layer is replaced by the silicon phosphide layer and then adhesion between copper and silicon nitride is improved. Moreover, the silicon phosphide comprises two advantages: low resistance than copper oxide and efficiently prevent copper diffuses into surrounding dielectric layer.

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A semiconductor fabrication method is provided for fabricating a dual damascene structure in a semiconductor device. By this method, a dielectric layer is first formed over a semiconductor substrate, and then a void structure including a via hole and a trench is formed in the dielectric layer. Next, a metallization structure is formed in the void structure in the dielectric layer, and after this, a special etching agent is used to treat the exposed surface of the metallization structure so as to make the exposed surface substantially rugged. Finally, a passivation layer is formed over the metallization structure, with the metallization structure serving as the intended dual damascene structure.

Abstract: The present invention provides a cleaning solution for cleaning a polishing pad used in a chemical-mechanical polishing (CMP) process for polishing the surface of a semiconductor wafer. The cleaning solution comprises a potassium hydroxide (KOH) solution for cleaning off slurry remaining on the surface of the polishing pad, and a hydrogen peroxide (H.sub.2 O.sub.2) solution and ammonia water (NH.sub.4 OH) solution for removing abrasive debris remaining on the surface of the polishing pad after the chemical-mechanical polishing process.

Abstract: A method of fabricating shallow trench isolation (STI) forms a trench in a substrate and a liner oxide layer in the trench. A first high density plasma chemical vapor deposition (HDPCVD) is performed to form a conformal oxide layer on the liner oxide layer, without applying bias to the substrate. A second HDPCVD is then performed to form an oxide layer that fills the trench and covers the conformal oxide layer on the conformal oxide layer.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A physical vapor deposition device comprises a vacuum chamber in which Ar ions are generated, a wafer chuck for holding a circular-shaped semiconductor wafer, a circular-shaped metal target above the wafer, an annular metal coil between the metal target and the wafer and made of the same material as the metal target, and a voltage controller for supplying voltage to the metal target, the wafer chuck and the metal coil. During a PVD processing, the voltage controller generates voltage biases between the metal target and the wafer chuck and between the metal coil and wafer chuck. That causes Ar ions to bombard the metal target to release metal atoms sputtering onto the center portion of the wafer, and causes Ar ions to bombard the metal coil to release the metal atoms sputtering onto the peripheral portion of the wafer so as to create a uniform metal layer on the wafer.

Abstract: A dual damascene structure includes a semiconductor substrate, a metal-oxide-semiconductor (MOS) transistor formed on the substrate and a metal layer. The metal layer is electrically connected to the conducting regions of the MOS transistor through interconnect. The metal layer further includes first metal spacing regions and second metal spacing regions, wherein the width of a first metal spacing region is about 1 to 10 times of the linewidth of the device, and the width of a second spacing region is about 0.8 to 1.2 times of the linewidth of the device. The first metal spacing regions includes a high-permittivity dielectric for a better thermal transferring rate, and the second spacing regions includes a low-permittivity dielectric for a shorter resistance-capacitance delay.

Abstract: An apparatus for controlling a uniformity of a polished material is described. An air bag comprises a plurality of tubular rings. An air-bag manifold controller is connected to the tubular rings. The air-bag manifold controller controls inflation and deflation of the tubular rings in order to draw up the polished material and control pressure difference between different areas of the polished material.

Abstract: A chemical-mechanical polishing station for polishing wafers. The polishing station comprises a slurry supplier, a polishing pad capable of collecting the slurry, and a polishing head capable of rotating a wafer and lowering the wafer onto the polishing pad in contact with the polishing pad and the slurry during a polishing session. The polishing head further includes a retaining ring for positioning the wafer. The retaining ring houses a light-emitting device capable of shining a beam of light onto the slurry and a light sensor for picking up the beam of light reflected back from the slurry. The exact polishing end-point can be decided by analyzing signals obtained from the light sensor.

Abstract: A chemical mechanical polishing apparatus for controlling slurry distribution is disclosed. The slurry flowing through the mesh before transferring to the polishing pad, the mesh being used to distribute the slurry onto surface of the polishing pad. There are different netting densities over the mesh, achieving the purpose of controlling slurry distribution.

Abstract: A method of forming a shallow trench isolation structure includes etching a substrate to form a trench. Then, an oxide layer is deposited in the trench and over the substrate by using high-density plasma. The oxide layer is pointed since it is formed by high-density plasma chemical vapor deposition. A stop layer made of silicon nitride, silicon oxy-nitride or boron nitride is formed on the oxide layer. The hardness of the stop layer is higher than that of the oxide layer so the protuberance of the oxide layer will be first removed during chemical mechanical polishing.