Abstract: A request to write host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination of a first status associated with the host data is made. The redundancy metadata associated with the host data is updated to indicate at least the first status associated with the host data. A memory access operation is performed to write the host data and the updated redundancy metadata to the memory device.

Abstract: Various aspects of the present disclosure relate to determining data migration priorities in a memory sub-system. A processing device performs a scan operation, such as a read disturb scan, to detect one or more errors in a memory block of the plurality of memory blocks. The processing device determines, based on a result of the scan operation, to perform a data migration operation to move data from one or more memory segments of the memory device to one or more other memory segments of the memory device, wherein the one or more memory segments of the memory device include at least one page of the memory block. The processing logic determines a corresponding priority level of the data migration operation. The processing logic performs the data migration operation based on the corresponding priority level.

Abstract: A method performed by a memory device to detect memory read errors is provided. The method comprises scanning a first memory cell associated with a first word line to obtain a first margin. The first word line is one of a list of word lines associated with target memory cells in a target memory block. The target memory cells are predetermined for scanning. The method further comprises determining if the first margin is lower than a triggering threshold, and in accordance with the determination, scanning a second memory cell associated with a second word line in the list of word lines associated with the target memory cells in the target memory block to obtain a second margin. The method further comprises marking the target memory block as bad upon determining that the second margin is lower than a folding threshold. The folding threshold is less than the triggering threshold.

Abstract: A memory sub-system includes a memory device and a processing device configured to: identify a first block family comprising a first plurality of blocks of the memory device that reside on a first set of die families of the memory device; identify a second block family comprising a second plurality of blocks of the memory device that reside on a second set of die families of the memory device; responsive to determining that the first set of die families of the memory device at least partially overlaps with the second set of die families of the memory device, determine a value of a similarity metric of the first block family and the second block family; and responsive to determining that the value of the similarity metric does not exceed a predefined similarity threshold, merge the first block family and the second block family.

Abstract: A memory sub-system includes a memory device and a processing device. The processing device is configured to: receive a read command specifying an identifier of a logical block and a page number; translate the identifier of the logical block into a physical address, the physical address comprising an identifier of a superblock and an identifier of a die; identify, based on block family metadata associated with the memory device, a superblock partition associated with the superblock, the page number, and the die; identify, based on the block family metadata, a block family associated with the superblock partition; determine a read voltage offset associated with the block family and the die; computing a modified read voltage by applying the read voltage offset to a base read level associated with the die; and read, using the modified read voltage, data from a physical page identified by the page number within the superblock.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to: identify a block family comprising a plurality of blocks of the memory device; responsive to determining that none of superblock partitions associated with the block family covers all die families of the set of die families, identify a combination of two or more superblock partitions associated with the block family, such that a union of die families covered by the combination of the two or more superblock partitions includes all die families of the set of die families of the memory device; and perform a scan operation with respect to the combination of the two or more superblock partitions.

Abstract: A system comprising a plurality of memory devices, as well as a processing device, operatively coupled with the plurality of memory devices. The processing device detects a write operation error during a write operation on a memory segment of the plurality of memory devices, wherein the memory segment comprises respective memory cells from each of the plurality of memory devices. The processing device determines that a back-to-back (B2B) count satisfies a B2B threshold criterion, wherein the B2B count corresponds to one of the plurality of memory devices. Responsive to determining that the B2B count satisfies the B2B threshold criterion, the processing device prevents, for a threshold duration of time, any subsequent write operations from being performed on the one of the plurality of memory devices, wherein a length of the threshold duration of time is determined by a period during which the B2B count continuously satisfies the B2B threshold criterion.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to: identify a block family comprising a plurality of blocks of the memory device; responsive to determining that none of superblock partitions associated with the block family covers all die families of the set of die families, identify a combination of two or more superblock partitions associated with the block family, such that a union of die families covered by the combination of the two or more superblock partitions includes all die families of the set of die families of the memory device; and perform a scan operation with respect to the combination of the two or more superblock partitions.

Abstract: Various example embodiments provide for early use of a redundant array of independent NAND-type memory devices-based (RAIN-based) error recovery technique in a read error handling (REH) process of a memory system to recover stored data. For some example embodiments, the RAIN-based error recovery technique is configured to determine, based on a system parameter, if and when the RAIN-based error recovery technique should be performed (e.g., triggered) at an alternative stage (e.g., at another position in the sequence) that is earlier than its current stage.

Abstract: A method for generating a virtual block stripe in a memory device is described. The method includes determining a minimum quantity of data blocks in the virtual block stripe to be generated and determining that a first bank has a first quantity of operational data blocks that is greater than the minimum quantity of data blocks in the virtual block stripe. The method also includes determining that a second bank has a second quantity of operational data blocks that is less than the minimum quantity of data blocks in the virtual block stripe and logically mapping one or more data blocks of the first bank to the second bank. The method further includes generating the virtual block stripe comprising the second quantity of operational data blocks of the second bank and the logically mapped one or more data blocks of the first bank.

Abstract: A method for performing a media scan operation in a memory device is described herein. The method includes initiating the media scan operation via a controller. The method also includes selecting one or more codewords that is a proper subset of a plurality of codewords in a page of memory via the controller. The method also includes determining a bit error count (BEC) of each of the one or more codewords via the controller. The method also includes comparing the BEC of each of the one or more codewords with a BEC threshold via the controller. The method further includes determining the BEC of each of the codewords of the page of memory via the controller in response to the BEC of one or more of the selected set of codewords being greater than the BEC threshold.

Abstract: A processing device in a memory sub-system determines a current temperature of a memory device and accesses historical transition data for management units at a plurality of temperatures. The processing device determines a transition time based on the historical transition data and current temperature, sets a scan frequency based on the transition time, and traverses management units at the scan frequency to maintain the management units in a transient state with lower raw bit error rate. The scan frequency may be set to be less than the transition time to prevent management units from transitioning to a stable state with higher raw bit error rate.

Abstract: Various embodiments provide handling block read-verify failure in a memory sub-system that supports zones. In particular, some embodiments described herein handle block read-verify failure during migration (e.g., copyback) of data from one or more cache blocks to one or more non-cache blocks of a zone on a memory device on a memory sub-system, during non-cache block (e.g., QLC non-cache block) refresh, or both.

Abstract: Various aspects of the present disclosure relate to determining data migration priorities in a memory sub-system. A processing device performs a scan operation, such as a read disturb scan, to detect one or more errors in a memory block of the plurality of memory blocks. The processing device determines, based on a result of the scan operation, to perform a data migration operation to move data from one or more memory segments of the memory device to one or more other memory segments of the memory device, wherein the one or more memory segments of the memory device include at least one page of the memory block. The processing logic determines a corresponding priority level of the data migration operation. The processing logic performs the data migration operation based on the corresponding priority level.

Abstract: Various embodiments provide handling block read failure in a memory sub-system that supports zones. In particular, some embodiments described herein handle block read failure during a data read (e.g., host data write) of a cache block or a non-cache block of a zone on a memory device on a memory sub-system, block read failure during refresh of a cache block or a non-cache block of a zone on a memory device on a memory sub-system, block read failure during migration of data between a cache block and a non-cache block of a zone on a memory device on a memory sub-system, or some combination thereof.

Abstract: Methods, systems, and apparatuses include probabilistically determining a read operation number using a window size. A read command is received from a host device by a memory subsystem. A memory address is determined using the read command. It is determined that the read command corresponds to the read operation number. The memory address is flagged to have a select gate of the memory address scanned. The select gate of the memory address is scanned in response to flagging the memory address.

Abstract: A system comprising a plurality of memory devices, as well as a processing device, operatively coupled with the plurality of memory devices. The processing device detects a write operation error during a write operation on a memory segment of the plurality of memory devices, wherein the memory segment comprises respective memory cells from each of the plurality of memory devices. The processing device determines that a back-to-back (B2B) count satisfies a B2B threshold criterion, wherein the B2B count corresponds to one of the plurality of memory devices. Responsive to determining that the B2B count satisfies the B2B threshold criterion, the processing device prevents, for a threshold duration of time, any subsequent write operations from being performed on the one of the plurality of memory devices, wherein a length of the threshold duration of time is determined by a period during which the B2B count continuously satisfies the B2B threshold criterion.

Abstract: Various aspects of the present disclosure relate to a memory sub-system for block stripe selection and testing. A processing device determines to perform a test for a subset of block stripes of a plurality of block stripes of the memory device, where each block stripe of the plurality of block stripes spans the plurality of dies of the memory device, and the subset of block stripes includes less than all block stripes of the plurality of block stripes. The processing device obtains a first parameter that indicates a first block stripe to be tested and a second parameter that indicates a quantity of block stripes to be tested. The processing device initiates and performs the test for the subset of block stripes using the first parameter and the second parameter.

Abstract: Various embodiments provide handling block program failure in a memory sub-system that supports zones. In particular, some embodiments described herein handle block program failure during a data write (e.g., host data write) to a cache block of a zone on a memory device on a memory sub-system, block program failure during refresh of a cache block of a zone on a memory device on a memory sub-system, block program failure during migration of data between a cache block and a non-cache block of a zone on a memory device on a memory sub-system, block program failure during refresh of a non-cache block of a zone on a memory device on a memory sub-system, or some combination thereof.

Abstract: Methods, systems, and devices for redundant array of independent not-AND (RAIN) block retirement handling are described. A memory system may implement techniques to avoid the preemptive retirement of a block of a memory device. In some examples, the memory system may count a quantity of bit errors for each block while performing a recovery procedure, such as a RAIN procedure. The memory system may determine that the quantity of bit errors satisfies a threshold for multiple blocks, which indicate that the error that triggered the recovery procedure may have been caused by intrinsic stress at the memory system, and the memory system may refrain from retiring the block. In some examples, the memory system may compare the corrected data with raw data read using stored read settings from a failed read operation, and the memory system may determine whether to retire the block based on the comparison.