Patents by Inventor Juane Li
Juane Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143232Abstract: A partition command from one of a plurality of write partition command queues or a plurality of read partition command queues is received. The received partition command is issued to a command processor of the sequencer component to be applied to one of the one or more memory devices. Responsive to receiving the partition command of the plurality of write partition command queues, whether a timeout threshold criterion pertaining to the plurality of read partition command queues is satisfied is determined. Responsive to determining that the timeout threshold criterion pertaining to the plurality of read partition command queues is not satisfied, whether a write threshold criterion pertaining to the plurality of write partition command queues is satisfied is determined.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Inventors: Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao, Jiangli Zhu
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Publication number: 20240126480Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive, from a host system, a command of a type; determine a weighted count of the command according to the type of the command; track, based on the weighted count, a first count of commands of the type; determine whether the first count of commands of the type satisfies a threshold criterion for commands of the type; and responsive to determining that the first count of commands of the type satisfies the threshold criterion, transmit a notification to the host system to refrain from transmitting commands of the type.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Inventors: Jason Duong, Fangfang Zhu, Jiangli Zhu, Juane Li, Chih-Kuo Kao
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Patent number: 11934657Abstract: A method for tracking open blocks in a memory device includes partitioning, by a memory sub-system controller, a storage region in the memory device into a plurality of channels, each channel including a plurality of planesets, and each planeset comprising a plurality of blocksets. The method further includes distributing evenly between the plurality of channels a plurality of active zones ready for a write operation. Each active zone includes one or more open blocks. The method further includes sending, by the memory sub-system controller, an open block message to a controller in the memory device, the open block message including channel identifying information, planeset identifying information, and blockset identifying information. The channel identifying information, the planeset identifying information, and the blockset identifying information collectively identify one or more open blocks ready for a write operation in the memory device.Type: GrantFiled: August 16, 2022Date of Patent: March 19, 2024Assignee: Micron Technology, Inc.Inventors: Michael Winterfeld, Juane Li
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Patent number: 11929763Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).Type: GrantFiled: March 29, 2021Date of Patent: March 12, 2024Assignee: WESTHOLD CORPORATIONInventors: Shu Lin, Khaled Ahmed Sabry Abdel-Ghaffar, Juane Li, Keke Liu
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Publication number: 20240078048Abstract: A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Inventors: Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao, Jiangli Zhu
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Publication number: 20240069748Abstract: A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page.Type: ApplicationFiled: July 6, 2023Publication date: February 29, 2024Inventors: Tingjun Xie, Yang Liu, Jiangli Zhu, Juane Li, Aaron Lee
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Publication number: 20240071462Abstract: A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.Type: ApplicationFiled: July 27, 2023Publication date: February 29, 2024Inventors: Tingjun Xie, Yang Liu, Juane Li, Aaron Lee, Jiangli Zhu
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Publication number: 20240061575Abstract: A method for tracking open blocks in a memory device includes partitioning, by a memory sub-system controller, a storage region in the memory device into a plurality of channels, each channel including a plurality of planesets, and each planeset comprising a plurality of blocksets. The method further includes distributing evenly between the plurality of channels a plurality of active zones ready for a write operation. Each active zone includes one or more open blocks. The method further includes sending, by the memory sub-system controller, an open block message to a controller in the memory device, the open block message including channel identifying information, planeset identifying information, and blockset identifying information. The channel identifying information, the planeset identifying information, and the blockset identifying information collectively identify one or more open blocks ready for a write operation in the memory device.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Michael Winterfeld, Juane Li
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Publication number: 20240062840Abstract: A processing device in a memory sub-system performs a first pass of a multi-pass programming operation to coarsely program a first wordline, performs a second pass to coarsely program a second wordline adjacent to the first wordline, performs a third pass of a multi-pass programming operation to finely program the first wordline, performs a fourth pass of a multi-pass programming operation to coarsely program a third wordline adjacent to the second wordline, performs a fifth pass of a multi-pass programming operation to finely program the second wordline, and responsive to determining that at least the second wordline has been finely programmed, performs a read verify operation on one or more cells associated with the first wordline.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Michael Winterfeld, Byron D. Harris, Tom Geukens, Juane Li, Fangfang Zhu
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Patent number: 11899972Abstract: A partition command from one of a plurality of write partition command queues or a plurality of read partition command queues is received. The received partition command is issued to a command processor of the sequencer component to be applied to one of the one or more memory devices. Responsive to receiving the partition command of the plurality of write partition command queues, whether a timeout threshold criterion pertaining to the plurality of read partition command queues is satisfied is determined. Responsive to determining that the timeout threshold criterion pertaining to the plurality of read partition command queues is not satisfied, whether a write threshold criterion pertaining to the plurality of write partition command queues is satisfied is determined.Type: GrantFiled: August 19, 2021Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao, Jiangli Zhu
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Publication number: 20240046990Abstract: Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.Type: ApplicationFiled: August 3, 2022Publication date: February 8, 2024Inventors: Yu-Chung LIEN, Juane LI, Sead ZILDZIC, JR., Zhenming ZHOU
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Patent number: 11893280Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.Type: GrantFiled: August 27, 2021Date of Patent: February 6, 2024Assignee: Micron Technology, Inc.Inventors: Jason Duong, Fangfang Zhu, Jiangli Zhu, Juane Li, Chih-Kuo Kao
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Patent number: 11860732Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.Type: GrantFiled: August 27, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Juane Li, Fangfang Zhu, Seungjune Jeon, Yueh-Hung Chen
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Publication number: 20230409210Abstract: A stripe-based command pertaining to a set of host data items at management units (MUs) of a memory sub-system configured to support non-stripe based commands is received. A set of operations to be executed at the MUs based on the stripe-based command is determined. The set of operations include one or more first operations associated with the set of host data items, the one or more first operations having a first type, and one or more second operations associated with the set of host data items, the one or more second operations having a second type. A first set of commands corresponding to the one or more first operations and a second set of commands corresponding to the one or more second operations is executed.Type: ApplicationFiled: August 31, 2023Publication date: December 21, 2023Inventors: Juane Li, Fangfang Zhu, Jiangli Zhu
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Patent number: 11847349Abstract: A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.Type: GrantFiled: August 19, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao, Jiangli Zhu
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Patent number: 11775216Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including receiving a media access operation access command to perform a media access operation with respect to a memory location residing on the memory device, determining whether there exists another memory location access at the memory location, in response to determining that another memory location access exists at the memory location, determining whether the media access operation command is a read command, and in response to determining that the media access operation is a read command, servicing the media access operation command from a media buffer. The media buffer maintains data associated with the completed write operation.Type: GrantFiled: August 30, 2021Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Jiangli Zhu, Juane Li
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Patent number: 11775179Abstract: A request to program a set of host data items to management units (MUs) of a fault tolerant stripe associated with a memory sub-system is received. A set of memory access operations to be executed at the MUs of the fault tolerant stripe in accordance with the received request is determined. The set of memory access operations include one or more read operations to read data from the MUs of the fault tolerant stripe. The set of memory access operations also include one or more write operations to write the set of host data items and redundancy metadata associated with the set of host data items to MUs of the fault tolerant stripe. A first series of commands corresponding to the one or more read operations of the set of memory access operations is executed. The redundancy metadata associated with the set of host data items is generated based on the data read from the MUs of the fault tolerant stripe during execution of the first series of commands and the set of host data items.Type: GrantFiled: August 27, 2021Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Juane Li, Fangfang Zhu, Jiangli Zhu
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Publication number: 20230251927Abstract: A request to write host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination of a first status associated with the host data is made. The redundancy metadata associated with the host data is updated to indicate at least the first status associated with the host data. A memory access operation is performed to write the host data and the updated redundancy metadata to the memory device.Type: ApplicationFiled: April 12, 2023Publication date: August 10, 2023Inventors: Seungjune Jeon, Juane Li, Ning Chen
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Publication number: 20230244822Abstract: Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.Type: ApplicationFiled: February 22, 2023Publication date: August 3, 2023Inventors: Juane Li, Jiangli Zhu, Ying Yu Tai
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Patent number: 11709631Abstract: A system includes a processing device, operatively coupled with a memory device, to perform operations including receiving a media access operation command designating a first memory location, and determining whether a first media access operation command designating the first memory location and a second media access operation designating a second memory location are synchronized, after determining that the first and second media access operation commands are not synchronized, determining that the media access operation command is an error flow recovery (ERF) read command, in response to determining that the media access operation command is an ERF read command, determining whether a head command of the first queue is blocked from execution, and in response to determining that the head command is unblocked from execution, servicing the ERF read command from a media buffer maintaining previously written ERF data.Type: GrantFiled: August 30, 2021Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Jiangli Zhu, Juane Li