Patents by Inventor Juane Li

Juane Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11709622
    Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Juane Li, Seungjune Jeon, Jiangli Zhu, Ying Tai
  • Patent number: 11709729
    Abstract: System and methods are disclosed including a plurality of memory devices and a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising: receiving, from a host system, encrypted write data appended with error-checking data; determining whether the encrypted write data contains an error based on the error-checking data; and responsive to determining that the encrypted write data contains an error, notifying the host system that the encrypted write data contains an error.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Juane Li, Fangfang Zhu, Jiangli Zhu, Ying Tai
  • Patent number: 11698867
    Abstract: A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seungjune Jeon, Fangfang Zhu, Juane Li, Jiangli Zhu, Ning Chen
  • Patent number: 11693597
    Abstract: A first command directed to a first package of a plurality of memory packages, wherein the first command is issued to a command processor to be applied to the first package is received. A total number of pending commands directed to the first package satisfies a first threshold criterion is determined. Responsive to determining that the total number of pending commands directed to the first package satisfies the first threshold criterion, whether a second command directed to a second package is requesting transmission is determined. Responsive to the second command directed to the second package is requesting transmission, whether the first command comprises a write command is determined. Responsive to determining that the first command comprises a write command, execute a command directed to the second package.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Juane Li, Jason Duong, Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu
  • Patent number: 11645147
    Abstract: First data is received. First error-checking data generated based on a cyclic redundancy check (CRC) operation of the first data is received. Second data is generated by combining the first data with a first data pattern. Second error-checking data of the second data is generated by using a combination of the first error-checking data and a second data pattern. The second data pattern has a size that is based on the first data pattern.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ning Chen, Juane Li
  • Patent number: 11636008
    Abstract: A request to program host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination is made, in view of the received request, whether the host data is valid data or invalid data. In response to a determination that the host data is invalid data, updated redundancy metadata associated with the host data is generated. The updated redundancy metadata indicates that the host data is invalid data. The host data and the updated redundancy metadata is programmed to the memory device.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seungjune Jeon, Juane Li, Ning Chen
  • Patent number: 11615214
    Abstract: Methods, systems, and devices for cryptographic key management are described. A memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. The memory device can generate, by a hardware component, the first cryptographic key based on the command. The memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. The memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Juane Li, Jiangli Zhu, Ying Yu Tai
  • Publication number: 20230082636
    Abstract: A system and method for recovery data generation for partial memory block modifications. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a command to modify a portion of a memory block that is stored by the memory device, wherein the command comprises user data and a location in the memory block; reading user data at the location and existing recovery data for the memory block; generating recovery data for the memory block based on the existing recovery data, the user data at the location, and the user data of the command; and writing the user data of the command and the generated recovery data to the memory device, wherein the user data overwrites the portion of the memory block at the location.
    Type: Application
    Filed: September 16, 2021
    Publication date: March 16, 2023
    Inventors: Jiangli Zhu, Ying Tai, Fangfang Zhu, Juane Li
  • Publication number: 20230061994
    Abstract: A request to program a set of host data items to management units (MUs) of a fault tolerant stripe associated with a memory sub-system is received. A set of memory access operations to be executed at the MUs of the fault tolerant stripe in accordance with the received request is determined. The set of memory access operations include one or more read operations to read data from the MUs of the fault tolerant stripe. The set of memory access operations also include one or more write operations to write the set of host data items and redundancy metadata associated with the set of host data items to MUs of the fault tolerant stripe. A first series of commands corresponding to the one or more read operations of the set of memory access operations is executed. The redundancy metadata associated with the set of host data items is generated based on the data read from the MUs of the fault tolerant stripe during execution of the first series of commands and the set of host data items.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Juane Li, Fangfang Zhu, Jiangli Zhu
  • Publication number: 20230066863
    Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Juane Li, Fangfang Zhu, Seungjune Jeon, Yueh-Hung Chen
  • Publication number: 20230064168
    Abstract: A system can include a memory device and a processing device coupled with the memory device. The processing device can receive a command of a first type from a host system. The processing device can select a threshold criterion for the command of the first type based on a count of commands of a second type. The processing device can determine whether a second count of commands of the first type satisfies the threshold criterion and in response to the second count satisfying the threshold criterion, the processing logic can transmit a notification to the host system to refrain from transmitting the commands of the first type.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Jason Duong, Fangfang Zhu, Jiangli Zhu, Juane Li, Chih-Kuo Kao
  • Publication number: 20230069122
    Abstract: A logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure are maintained. The L2P data structure comprises table entries that map a logical address to a physical address. The P2L data structure comprises data entries that map a physical address to a logical address. The P2L data entries also comprise a data move status, a base address, and a boundary indicator. A move operation is detected, wherein the move operation indicates that data referenced by a logical address is to be moved from a source physical address to a destination physical address. Responsive to detecting the move operation, the data move status associated with the source physical address in the P2L data structure is updated.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Seungjune Jeon, Fangfang Zhu, Juane Li, Jiangli Zhu, Ning Chen
  • Publication number: 20230067738
    Abstract: A request to program host data to a memory device of a memory sub-system is received. Redundancy metadata associated with the host data is generated. A determination is made, in view of the received request, whether the host data is valid data or invalid data. In response to a determination that the host data is invalid data, updated redundancy metadata associated with the host data is generated. The updated redundancy metadata indicates that the host data is invalid data. The host data and the updated redundancy metadata is programmed to the memory device.
    Type: Application
    Filed: September 1, 2021
    Publication date: March 2, 2023
    Inventors: Seungjune Jeon, Juane Li, Ning Chen
  • Publication number: 20230064282
    Abstract: A system includes a memory device, and a processing device, operatively coupled with the memory device, to perform operations including receiving a media access operation access command to perform a media access operation with respect to a memory location residing on the memory device, determining whether there exists another memory location access at the memory location, in response to determining that another memory location access exists at the memory location, determining whether the media access operation command is a read command, and in response to determining that the media access operation is a read command, servicing the media access operation command from a media buffer. The media buffer maintains data associated with the completed write operation.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Fangfang Zhu, Jiangli Zhu, Juane Li
  • Publication number: 20230064382
    Abstract: A system includes a processing device, operatively coupled with a memory device, to perform operations including receiving a media access operation command designating a first memory location, and determining whether a first media access operation command designating the first memory location and a second media access operation designating a second memory location are synchronized, after determining that the first and second media access operation commands are not synchronized, determining that the media access operation command is an error flow recovery (ERF) read command, in response to determining that the media access operation command is an ERF read command, determining whether a head command of the first queue is blocked from execution, and in response to determining that the head command is unblocked from execution, servicing the ERF read command from a media buffer maintaining previously written ERF data.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Fangfang Zhu, Jiangli Zhu, Juane Li
  • Publication number: 20230054363
    Abstract: A partition command from one of a plurality of write partition command queues or a plurality of read partition command queues is received. The received partition command is issued to a command processor of the sequencer component to be applied to one of the one or more memory devices. Responsive to receiving the partition command of the plurality of write partition command queues, whether a timeout threshold criterion pertaining to the plurality of read partition command queues is satisfied is determined. Responsive to determining that the timeout threshold criterion pertaining to the plurality of read partition command queues is not satisfied, whether a write threshold criterion pertaining to the plurality of write partition command queues is satisfied is determined.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao, Jiangli Zhu
  • Publication number: 20230056808
    Abstract: A first command directed to a first package of a plurality of memory packages, wherein the first command is issued to a command processor to be applied to the first package is received. A total number of pending commands directed to the first package satisfies a first threshold criterion is determined. Responsive to determining that the total number of pending commands directed to the first package satisfies the first threshold criterion, whether a second command directed to a second package is requesting transmission is determined. Responsive to the second command directed to the second package is requesting transmission, whether the first command comprises a write command is determined. Responsive to determining that the first command comprises a write command, execute a command directed to the second package.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Juane Li, Jason Duong, Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu
  • Publication number: 20230056287
    Abstract: A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Juane Li, Fangfang Zhu, Jason Duong, Chih-Kuo Kao, Jiangli Zhu
  • Publication number: 20230058232
    Abstract: A die command from a requestor is received. The die command into a die command queue is stored. The die command from the die command queue into a plurality of partition commands is partitioned. The plurality of partition commands into one of a first plurality of partition command queues or a second plurality of partition command queues is mapped. The partition command of the first plurality of partition command queues or the second plurality of partition command queues is issued to a command processor to be applied to the one or more memory devices.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Juane Li, Jason Duong, Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu
  • Patent number: 11567825
    Abstract: First and second data are identified, such that the second data is based on a modification operation performed on the first data. First error-checking data comprising a Cyclic Redundancy Check (CRC) value of the first data is identified. Incremental error-checking data is generated based on a difference between the first data and the second data. Updated first error-checking data is generated based on a combination of the first error-checking data and the incremental error-checking data. The updated first error-checking data is compared to second error-checking data generated from a CRC value of the second data to determine whether the second data contains an error.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ning Chen, Juane Li, Fangfang Zhu