Abstract: A data storage device and method for enabling endurance re-evaluation are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive data and a first storage requirement for the data from a host; store the data in a first group of memory cells in the memory, wherein the first group of memory cells satisfies the first storage requirement; receive a notification from the host that the first storage requirement has changed to a second storage requirement; and move the data from the first group of memory cells to a second group of memory cells in the memory, wherein the second group of memory cells satisfies the second storage requirement. Other embodiments are provided.

Abstract: Boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized. The controller is configured to track an HMB turnaround latency and derive whether a next request should be sent to the HMB or the memory device when the data is present in both the HMB and the memory device.

Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. The data storage device can guide a host device to select a particular zone to open in zone namespace (ZNS) systems where the host device selects which zone to open. The data storage device tracks the workload of the various storage locations and create zones. The data storage device then provides selected zones having the least used storage locations with the idea of guiding the host device to select the zone having the least used storage locations. Thus, rather than utilizing a randomly selected unopened zone, the host will select, based upon guidance from the data storage device, zones that contain the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.

Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. When receiving a zone open command in a zone namespace (ZNS) system, rather than randomly selecting an unopen zone, zones may be categorized based upon storage location workload so that any new zone that is opened utilizes the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.

Abstract: A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. When receiving a zone open command in a zone namespace (ZNS) system, rather than randomly selecting an unopen zone, zones may be categorized based upon storage location workload so that any new zone that is opened utilizes the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.

Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. The data storage device can guide a host device to select a particular zone to open in zone namespace (ZNS) systems where the host device selects which zone to open. The data storage device tracks the workload of the various storage locations and create zones. The data storage device then provides selected zones having the least used storage locations with the idea of guiding the host device to select the zone having the least used storage locations. Thus, rather than utilizing a randomly selected unopened zone, the host will select, based upon guidance from the data storage device, zones that contain the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.

Abstract: The present disclosure generally relates to aborting a command efficiently using the host memory buffer (HMB). The command contains pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.

Abstract: The present disclosure generally relates to systems and methods by which a data storage device may receive data about the host system in which it is installed, and the customer associated with that system. Based upon this received data, the data storage device may modify its native operating parameters and custom functions to enable more optimal operation with the host system.

Abstract: The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.

Abstract: Technology is disclosed for allocating PCIe bus bandwidth to storage commands in a peer-to-peer environment. A non-volatile storage system has a peer-to-peer connection with a host system and a target device, such as a GPU. A memory controller in the storage system monitors latency of PCIe transactions that are performed over a PCIe bus in order to transfer data for NVMe commands. The PCIe transactions may involve direct memory access (DMA) of memory in the host system or target device. There could be a significant difference in transaction latency depending on what memory is being accessed and/or what communication link is used to access the memory. The memory controller allocates bandwidth on a PCIe bus to the NVMe commands based on the latencies of the PCIe transactions. In an aspect, the memory controller groups the PCIe addresses based on the latencies of the PCIe transactions.

Abstract: A non-volatile storage system that is implementing a storage region (e.g., a persistent memory region) which is accessible to a host (e.g., via a PCIe connection) and a cache for the storage region shares details of the structure of the storage region and/or the cache (e.g., cache segment size). With awareness of the shared details of the structure of the storage region and/or the cache, the host arranges and sends out requests to read data from the persistent memory region in a manner that takes advantage of parallelism within the non-volatile storage system. For example, the host may initially send out one read request per cache segment to cause the non-volatile storage system to load the cache. Subsequently, additional read requests are made to the non-volatile storage system, with the data already loaded (or starting to load) in the cache, thereby increasing performance.

Abstract: A method and system for cache-based flow of a simple copy command is disclosed. The present disclosure generally relates to methods and systems for executing a simple copy command in a manner that mitigates additional latency in the device. According to certain embodiments, a copy command manager that includes one or more copy command slots is provided. When a simple copy command is received from a host, a copy command slot is allocated to the command, and the simple copy command is copied into the copy command slot. Upon copying the simple copy command to the copy command slot, an overlap table of the data storage device controller is updated to indicate the copy has been completed, and the completion is posted to the host. After posting, the simple copy command is carried out in the background through completion.

Abstract: A method and apparatus for enforcing privacy within one or more memories of a data storage system are disclosed. In one embodiment, sensor data containing personally identifiable information (PII) is provided to a memory. In some embodiments, the memory of disclosed systems and methods may be volatile, non-volatile, or a combination. Within the memory, PII is detected in some embodiments by AI-based computer vision, voice recognition, or natural language processing methods. Detected PII is obfuscated within the memory prior to making the sensor data available to other systems or memories. In some embodiments, once PII has been obfuscated, the original sensor data is overwritten, deleted, or otherwise made unavailable.

Abstract: A data storage device includes a memory device, an always on (AON) application specific integrated circuit (ASIC), and a controller coupled to the memory device and the AON ASIC. When the data storage device enters a low power state, the controller generates and stores security data associated with context data in a power management integrated circuit (PMIC). The context data is stored in both the memory device and a host memory buffer (HMB). A location of the context data in the HMB is stored in the PMIC with the security data. When the data storage device exits the low power state, the address stored in the PMIC is utilized to retrieve the context data from the HMB. The retrieved context data is verified against the security data by the controller.

Abstract: A storage device includes a controller that can dynamically adjust the zone active limit (ZAL) for a zoned namespace (ZNS). Rather than assuming a worst-case scenario for the ZNS, the ZAL can be dynamically adjusted, even after providing the ZAL to a host device. In so doing, device behavior changes due to factors such as temperature, failed or flipped bit count, and device cycling can be considered as impacting the ZAL. The ZAL can then be adjusted over time, and the new ZAL can be communicated to the host device. As such, rather than a fixed, worst-case ZAL, the host device will receive updated ZAL values over time as the device performs.

Abstract: The present disclosure generally relate to dynamically changing predictive latency related attributes to increase the deterministic window (DTWIN) of operation. The host device workload characteristics as well as the memory device's current condition provide valuable information for the duration of the DTWIN. If the memory device is near the end of life, then the DTWIN duration will be smaller. Additionally, if the workload from the host device is heavy, then the DTWIN duration will also be smaller. Rather than utilizing a fixed DTWIN duration based upon worst case scenarios for host device workload and memory device condition, dynamically adjusting the DTWIN duration based upon the workload and condition will provide a DTWIN duration that can gradually decrease over time from a much longer DTWIN duration than is currently available.

Abstract: The present disclosure generally relates to efficient block usage after ungraceful shutdown (UGSD) events. After a UGSD event, a host device is alerted by the data storage device that a QLC block that was being used prior to the UGSD event is experiencing an ongoing block recovery and that the block is not yet available to accept new data. The block is then checked to determine whether the block can continue to be used for the programming that was occurring at the time of the UGSD event. Once a determination is made, the data storage device notifies the host device so that normal operations may continue. Additionally, the amount of free blocks available for programming is monitored during UGSD events so that the host device can be warned if a power loss halt is triggered.

Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.