Patents by Inventor Judy Xilin An
Judy Xilin An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8580660Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: GrantFiled: June 14, 2012Date of Patent: November 12, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ren Lin, Judy Xilin An, Zoran Krivokapic, Cyrus E. Tabery, Haihong Wang, Bin Yu
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Patent number: 8334181Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.Type: GrantFiled: July 14, 2010Date of Patent: December 18, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
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Publication number: 20120252193Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Ming-Ren LIN, Judy Xilin AN, Zoran KRIVOKAPIC, Cyrus E. TABERY, Haihong WANG, Bin YU
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Patent number: 8222680Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.Type: GrantFiled: October 22, 2002Date of Patent: July 17, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Ming-Ren Lin, Judy Xilin An, Zoran Krivokapic, Cyrus E. Tabery, Haihong Wang, Bin Yu
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Patent number: 7781810Abstract: A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.Type: GrantFiled: October 3, 2006Date of Patent: August 24, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
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Patent number: 7679134Abstract: A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.Type: GrantFiled: January 12, 2004Date of Patent: March 16, 2010Assignee: GlobalfoundriesInventors: Matthew S. Buynoski, Judy Xilin An, Haihong Wang, Bin Yu
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Patent number: 7630850Abstract: A method for operating an integrated circuit tester information processing system includes: measuring current information from test structures for an integrated circuit having a stress liner; forming a transfer curve by simulating based on the current information with a first range of first mobility multipliers; forming an inverse transfer curve by applying an inverse transfer function to the transfer curve; forming a stress curve with second mobility multipliers from the inverse curve; and validating the second mobility multipliers by comparing a measured curve and a simulated curve with the measured curve based on the current information and the simulated curve based on stress curve.Type: GrantFiled: October 15, 2007Date of Patent: December 8, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Rasit Onur Topaloglu, Judy Xilin An
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Patent number: 7610160Abstract: A method for operating an integrated circuit tester information processing system includes measuring current information from test structures for an integrated circuit having dual stress liners; selecting currents from the current information or stored current information; deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and correlating the stress contribution with the integrated circuit.Type: GrantFiled: September 18, 2007Date of Patent: October 27, 2009Assignee: GlobalFoundries Inc.Inventors: Sushant S. Suryagandh, Judy Xilin An
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Publication number: 20090099829Abstract: A method for operating an integrated circuit tester information processing system includes: measuring current information from test structures for an integrated circuit having a stress liner; forming a transfer curve by simulating based on the current information with a first range of first mobility multipliers; forming an inverse transfer curve by applying an inverse transfer function to the transfer curve; forming a stress curve with second mobility multipliers from the inverse curve; and validating the second mobility multipliers by comparing a measured curve and a simulated curve with the measured curve based on the current information and the simulated curve based on stress curve.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Rasit Onur Topaloglu, Judy Xilin An
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Publication number: 20090076750Abstract: A method for operating an integrated circuit tester information processing system includes measuring current information from test structures for an integrated circuit having dual stress liners; selecting currents from the current information or stored current information; deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and correlating the stress contribution with the integrated circuit.Type: ApplicationFiled: September 18, 2007Publication date: March 19, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Sushant S. Suryagandh, Judy Xilin An
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Patent number: 7432557Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.Type: GrantFiled: January 13, 2004Date of Patent: October 7, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Matthew S. Buynoski, Judy Xilin An, Bin Yu
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Patent number: 7432558Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a <100> orientation. A first gate may be formed on the insulating layer proximate to the side surface of the fin.Type: GrantFiled: June 9, 2004Date of Patent: October 7, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Bin Yu
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Patent number: 7259425Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.Type: GrantFiled: January 23, 2003Date of Patent: August 21, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Judy Xilin An, Haihong Wang, Bin Yu
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Patent number: 7179692Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.Type: GrantFiled: August 9, 2004Date of Patent: February 20, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Bin Yu, Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Zoran Krivokapic, Haihong Wang
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Patent number: 7148526Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.Type: GrantFiled: January 23, 2003Date of Patent: December 12, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
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Patent number: 6960804Abstract: A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.Type: GrantFiled: October 10, 2003Date of Patent: November 1, 2005Assignee: Hussman CorporationInventors: Chih-Yuh Yang, Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Bin Yu
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Patent number: 6921963Abstract: A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.Type: GrantFiled: April 23, 2004Date of Patent: July 26, 2005Assignee: Advanced Micro Devices, IncInventors: Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina-Murthy, Haihong Wang, Bin Yu
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Patent number: 6911697Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin, source and drain regions and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The source region is formed on the insulating layer adjacent a first side of the fin and the drain region is formed on the second side of the fin opposite the first side. The source and drain regions have a greater thickness than the fin in the channel region of the semiconductor device.Type: GrantFiled: August 4, 2003Date of Patent: June 28, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Judy Xilin An, Bin Yu
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Patent number: 6897527Abstract: A semiconductor device includes a fin and a layer formed on at least a portion of the fin. The fin includes a first crystalline material. The layer includes a second crystalline material, where the first crystalline material has a larger lattice constant than the second crystalline material to induce tensile strain within the layer.Type: GrantFiled: April 28, 2004Date of Patent: May 24, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Srikanteswara Dakshina-Murthy, Judy Xilin An, Zoran Krivokapic, Haihong Wang, Bin Yu
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Patent number: 6872647Abstract: A method of forming multiple fins in a semiconductor device includes forming a structure having an upper surface and side surfaces on the semiconductor device. The semiconductor device includes a conductive layer located below the structure. The method also includes forming spacers adjacent the structure and selectively etching the spacers and the conductive layer to form the fins. The fins may be used in a FinFET device.Type: GrantFiled: May 6, 2003Date of Patent: March 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Bin Yu, Judy Xilin An, Cyrus E. Tabery