Patents by Inventor Juergen Haess

Juergen Haess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9170771
    Abstract: A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Maarten Boersma, Juergen Haess
  • Patent number: 8984039
    Abstract: A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Maarten Jakob Boersma, Juergen Haess
  • Patent number: 8909994
    Abstract: A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Juergen Haess, Michael K. Kroener, Silvia M. Mueller
  • Patent number: 8892958
    Abstract: In a data processing system a plurality of signals associated with an operation are received during execution of the operation. In response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selects and outputs as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selects and outputs as the trace signal a second signal of the plurality of signals.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Juergen Haess, Michael K. Kroener, Silvia M. Mueller
  • Publication number: 20140164463
    Abstract: A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JUERGEN HAESS, MICHAEL K. KROENER, SILVIA M. MUELLER, KERSTIN SCHELM
  • Publication number: 20140095941
    Abstract: A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals.
    Type: Application
    Filed: December 3, 2013
    Publication date: April 3, 2014
    Inventors: STEVEN R. CARLOUGH, JUERGEN HAESS, MICHAEL K. KROENER, SILVIA M. MUELLER
  • Publication number: 20130339417
    Abstract: A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juergen Haess, Michael K. Kroener, Silvia M. Mueller, Kerstin Schelm
  • Publication number: 20130339802
    Abstract: A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: International Business Machines Corporation
    Inventors: Steven R. Carlough, Juergen Haess, Michael K. Kroener, Silvia M. Mueller
  • Publication number: 20130204916
    Abstract: A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 8, 2013
    Applicant: International Business Machines Corporation
    Inventors: Maarten Boersma, Juergen Haess
  • Patent number: 7730117
    Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Juergen Haess, Michael Kroener, Martin S. Schmookler, Eric M. Schwarz, Son Dao-Trong
  • Patent number: 7716266
    Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Son Dao Trong, Juergen Haess, Klaus Michael Kroener, Eric M. Schwarz
  • Patent number: 7461117
    Abstract: The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of t
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Son Dao Trong, Juergen Haess, Christian Jacobi, Klaus Michael Kroener, Silvia Melitta Mueller, Jochen Preiss
  • Patent number: 7392273
    Abstract: Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LAB) of the addend in a dedicated circuit right at the beginning of the pipe. LAB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LAB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Guenter Gerwig, Juergen Haess, Klaus Michael Kroener
  • Patent number: 7188233
    Abstract: A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Juergen Haess, Michael Kroener, Dung Quoc Nguyen, Lawrence J. Powell, Jr., Eric M. Schwarz, Son Dao-Trong, Raymond C. Yeung
  • Publication number: 20060184603
    Abstract: The present invention relates to a method and circuit for performing multiply-operations in an arithmetic unit of a computer processor. In a multiplier thereof, zero detection of the resulting product bit string (22) is needed for a proper setting of condition code and overflow status information. Zero detection according to prior art decreases the calculation speed in the multiplier. In order to provide a method and respective electronic circuit, wherein the zero detection is earlier completed, it is proposed to use a leading zero anticipation (LZA) hardware—i.e., an LZA circuit (40), which exists usually anyway in floating point processor adders for calculating the number of leading zeros for operand normalization purposes—for performing a zero detection of the product by aid of the partial results (16, 17) emerging at the output of the Wallace tree of the multiplier.
    Type: Application
    Filed: February 11, 2005
    Publication date: August 17, 2006
    Inventors: Son Trong, Mark Erle, Bruce Fleischer, Juergen Haess, Michael Kelly, Klaus Kroener, Martin Schmookler, Eric Schwarz
  • Publication number: 20060184601
    Abstract: The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of t
    Type: Application
    Filed: February 11, 2005
    Publication date: August 17, 2006
    Inventors: Son Trong, Juergen Haess, Christian Jacobi, Klaus Kroener, Silvia Mueller, Jochen Preiss
  • Publication number: 20060179286
    Abstract: A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Juergen Haess, Michael Kroener, Dung Nguyen, Eric Schwarz, Son Dao-Trong, Raymond Yeung
  • Publication number: 20060179100
    Abstract: A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Juergen Haess, Michael Kroener, Dung Nguyen, Lawrence Powell, Eric Schwarz, Son Dao-Trong, Raymond Yeung
  • Publication number: 20060179097
    Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
    Type: Application
    Filed: February 9, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Bruce Fleischer, Juergen Haess, Michael Kroener, Martin Schmookler, Eric Schwarz, Son Dao-Trong
  • Publication number: 20060179096
    Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
    Type: Application
    Filed: February 10, 2005
    Publication date: August 10, 2006
    Applicant: International Business Machines Corporation
    Inventors: Bruce Fleischer, Juergen Haess, Michael Kroener, Robert Montoye, Martin Schmookler, Eric Schwarz, Son Dao-Trong