Patents by Inventor Juergen Haess

Juergen Haess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060173946
    Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).
    Type: Application
    Filed: January 26, 2006
    Publication date: August 3, 2006
    Applicant: International Business Machines Corporation
    Inventors: Son Trong, Juergen Haess, Klaus Kroener, Eric Schwarz
  • Patent number: 7085865
    Abstract: The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Juergen Haess, Ingemar Holm, Hartmut Ulland, Gerhard Zilles
  • Publication number: 20050060454
    Abstract: The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention further enables bus arbitration during a first transmission since that the bus can be granted for a second transmission following the first transmission without wasting bus cycles. This is accomplished by determining the number of cycles remaining for the first transmission according to memory boundary and transmission packet boundary conditions.
    Type: Application
    Filed: July 21, 2004
    Publication date: March 17, 2005
    Applicant: International Business Machines Corporation
    Inventors: Juergen Haess, Ingemar Holm, Hartmut Ulland, Gerhard Zilles
  • Publication number: 20040122886
    Abstract: Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall Multiply/Add processing. Parts of the intermediate add result are significant and have to be selected in the pre-normalizer multiplexer to be fed to the normalizer by counting the leading zero bits (LZB) of the addend in a dedicated circuit right at the beginning of the pipe. LZB is added to the shift amount (SA) that is calculated to align the addend and is then compared with the width of the incrementer. If the sum of (SA+LZB) is larger than the width of the incrementer, which is a constant value, then no significant bits are in the high-part of the intermediate result, and the pre-normalizer multiplexer selects the data from a second predetermined position, otherwise from a first predetermined position.
    Type: Application
    Filed: December 10, 2003
    Publication date: June 24, 2004
    Applicant: International Business Machines Corporation
    Inventors: Guenter Gerwig, Juergen Haess, Klaus Michael Kroener
  • Patent number: 6694344
    Abstract: A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: February 17, 2004
    Assignee: International Business Machines Corporation
    Inventors: Guenter Gerwig, Juergen Haess, Michael Kroener, Erwin Pfeffer
  • Patent number: 5524270
    Abstract: A system buffers first and second data buses having asynchronous, different frequency clocks. The system comprises a data buffer interposed between the first and second data buses to receive data from the first bus and supply data to the second bus. The also comprises a write address generator, coupled to the first bus to receive a data available signal and coupled to the data buffer, for generating an address in the data buffer to store the data received from the first bus. The data available signal increments the write address generator. A load record register is coupled to receive an indication that data is being written from the first data bus into the data buffer, and tracks locations in the data buffer which have received data from the first data bus. A read address generator is coupled to the data buffer, and generates an address of the next data, if any, that is stored in the data buffer to be read onto the second data bus.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: June 4, 1996
    Assignee: International Business Machines Corporation
    Inventors: Juergen Haess, Rolf Hilgendorf