Patents by Inventor Jui-Chien Huang
Jui-Chien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12218226Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of channel layers stacked over a semiconductor substrate and spaced apart from one another, a source/drain structure adjoining the plurality of channel layers, a gate structure wrapping around the plurality of channel layers, and a first inner spacer between the gate structure and the source/drain structure and between the plurality of channel layers. The first inner spacer is made of an oxide of a semiconductor material.Type: GrantFiled: October 27, 2020Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Hao Wang, Kuo-Cheng Ching, Jui-Chien Huang
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Patent number: 12198986Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.Type: GrantFiled: August 7, 2023Date of Patent: January 14, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Sheng Yun, Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Chao Chou, Chun-Hsiung Lin, Pei-Hsun Wang
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Publication number: 20240413019Abstract: A method includes forming a first transistor in a first wafer, wherein the first transistor includes a first source/drain region, forming a first bond pad electrically coupling to the first source/drain region, forming an second transistor in a second wafer, wherein the second transistor includes a second source/drain region, forming a second bond pad electrically coupling to the second source/drain region, and bonding the second wafer to the first wafer, with the second bond pad being bonded to the first bond pad.Type: ApplicationFiled: January 2, 2024Publication date: December 12, 2024Inventors: Ting-Yun Wu, Jui-Chien Huang, Szuya Liao
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Publication number: 20240413156Abstract: A method includes forming a lower transistor in a lower wafer, wherein the lower transistor includes a lower source/drain region, forming a contact plug electrically connecting to the lower source/drain region, and forming a metal line over the lower transistor. A first portion of the metal line is vertically aligned to the lower source/drain region. The method further includes bonding an upper wafer to the lower wafer, and forming an upper transistor in the upper wafer. The upper transistor includes an upper source/drain region, and is vertically aligned to a second portion of the metal line. A first interconnect structure is formed on the lower wafer and electrically connecting to the lower transistor. A second interconnect structure is formed on the upper wafer and electrically connecting to the upper transistor.Type: ApplicationFiled: November 7, 2023Publication date: December 12, 2024Inventors: Ting-Yun Wu, Jui-Chien Huang, Szuya Liao
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Publication number: 20240387287Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang
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Patent number: 12148812Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.Type: GrantFiled: July 26, 2022Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
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Patent number: 12148673Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.Type: GrantFiled: August 1, 2023Date of Patent: November 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Wang, Jui-Chien Huang, Kuo-Cheng Ching, Chun-Hsiung Lin, Pei-Hsun Wang
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Publication number: 20240379874Abstract: A transistor includes a gate structure, a spacer laterally surrounding the gate structure. a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, and a source/drain contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Ching Cheng, Jui-Chien Huang, Yi-Tse Hung, Shih Hao Wang, Han Wang, Szuya LIAO
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Publication number: 20240381610Abstract: The first semiconductor layer and the second semiconductor layer are above the first semiconductor layer, in which the first and second semiconductor layers are vertically spaced apart from each other. The first and second source/drain epitaxial features are respectively on first and second sides of the first semiconductor layer. The third and fourth source/drain epitaxial features are respectively on first and second sides of the second semiconductor layer and above the first source/drain epitaxial feature. The first, third, and fourth source/drain epitaxial features have a first conductive type, and the second source/drain epitaxial feature has a second conductive type opposite to the first conductive type.Type: ApplicationFiled: May 10, 2023Publication date: November 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yin WANG, Wei-Xiang YOU, Kao-Cheng LIN, Jui-Chien HUANG, Szuya LIAO
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Publication number: 20240347391Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang, Kuo-Cheng Chiang, Kuan-Lun Cheng
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Publication number: 20240313118Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: ApplicationFiled: May 24, 2024Publication date: September 19, 2024Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20240258314Abstract: A method for forming complementary FinFET (CFET) in a stacked configuration includes forming a recess in a stacked fin, growing a first epitaxial structure in the recess, etching the first epitaxial structure to remove a portion of the first epitaxial structure, forming a first isolation structure over the first epitaxial structure, and forming a second epitaxial structure over the first isolation structure. In another method, a dummy gate electrode over the stacked fin is etched, a first gate electrode deposited over the stacked fin, a portion of the first gate electrode recessed, and a second gate electrode formed over the first gate electrode. A CFET device includes a second channel region stacked over a first channel region, associated pairs of epitaxial structures on opposing sides of each of the first and second channel regions, and associated gate electrodes for each of the first and second channel regions.Type: ApplicationFiled: May 25, 2023Publication date: August 1, 2024Inventors: Ting-Yun Wu, Jui-Chien Huang, Szuya Liao
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Publication number: 20240250029Abstract: Semiconductor devices including a first upper channel structure, a first intermediate structure below the first upper channel structure, a first lower channel structure below the first intermediate structure, and a voltage source connected to the first lower channel structure, in which the first upper channel structure, the first intermediate structure, and the first lower channel structure comprise a first vertical assembly that provides an electrical connection between the voltage source and the first upper channel structure.Type: ApplicationFiled: August 21, 2023Publication date: July 25, 2024Inventors: Kao-Cheng LIN, Jui-Chien HUANG, Pin-Dai SUE, Yen-Huei CHEN
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Publication number: 20240234404Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.Type: ApplicationFiled: January 11, 2023Publication date: July 11, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Cheng TZENG, Shih-Wei PENG, Ching-Yu HUANG, Chun-Yen LIN, Wei-Cheng LIN, Jiann-Tyng TZENG, Szuya LIAO, Jui-Chien HUANG, Cheng-Yin WANG, Ting-Yun WU
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Patent number: 12033899Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.Type: GrantFiled: April 24, 2023Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang, Kuo-Cheng Chiang, Kuan-Lun Cheng
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Publication number: 20240213195Abstract: A semiconductor structure includes a first device assembly and a second device assembly. Each of the first and second device assembly includes a substrate, a main unit disposed on the substrate and including at least one device, a dielectric unit disposed on the main unit and having an interconnecting surface opposite to the substrate, and an electrically conductive routing disposed in the dielectric unit, electrically connected to the at least one device, and including an end portion. The interconnecting surface of the dielectric unit of the first device assembly is bonded to the interconnecting surface of the dielectric unit of the second device assembly such that the end portion of the electrically conductive routing of the first device assembly is in direct contact with the end portion of the electrically conductive routing of the second device assembly. A method for manufacturing the semiconductor structure are also disclosed.Type: ApplicationFiled: February 24, 2023Publication date: June 27, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-De HO, Wei-Xiang YOU, Jui-Chien HUANG, Szuya LIAO
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Publication number: 20240194735Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.Type: ApplicationFiled: February 23, 2024Publication date: June 13, 2024Inventors: GUAN-LIN CHEN, KUO-CHENG CHIANG, CHIH-HAO WANG, SHI NING JU, JUI-CHIEN HUANG
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Patent number: 12009216Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.Type: GrantFiled: July 25, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
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Patent number: 11996483Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: GrantFiled: December 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Patent number: 11942478Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.Type: GrantFiled: May 6, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen