Abstract: An LDMOS device includes: a semiconductor layer formed over a semiconductor substrate; a gate structure disposed over the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure; a second doped region disposed in the semiconductor layer adjacent to a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the semiconductor layer under in the first doped region; an insulating layer covering the third doped region, the gate structure, and the fourth doped region; a conductive layer conformably formed over a bottom surface and sidewalls of the trench; a dielectric layer disposed in the trench; and a diffused region disposed in the semiconductor layer under the trench.

Abstract: A light-emitting diode (LED) and fabricating method thereof. The method includes: providing a first substrate and forming an epitaxial portion on the first substrate; forming at least one reflection layer on the epitaxial portion; forming a metal barrier portion on the reflection layer; etching the epitaxial portion and the barrier portion by a first etching process, so as to form a plurality of epitaxial layers and a plurality of metal barrier layers, an etch channel is formed between adjacent epitaxial layers, and each metal barrier layer enwraps a corresponding reflection layer and covers all of a surface of a corresponding epitaxial layer; forming a first bonding layer on the metal barrier layer; and forming a second substrate on the first bonding layer and removing the first substrate.

Abstract: A light-emitting diode (LED) device, includes a substrate, having a first and a second surfaces, a first bonding layer, disposed on the first surface, a first epitaxial structure, having a third and a fourth surfaces and comprising a first and a second groove, wherein the first epitaxial structure comprises a second electrical type semiconductor layer, an active layer and a first electrical type semiconductor layer sequentially stacked on the first bonding layer, and the first groove extends from the fourth surface to the first electrical type semiconductor layer via the active layer, the second groove extends from the fourth surface to the third surface, a first electrical type conductive branch, a first electrical type electrode layer, an insulating layer, filled in the first and the second grooves, and a second electrical type electrode layer, electrically connected to the second electrical type semiconductor layer.

Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: A semiconductor device is provided. A substrate is provided. A buried layer is formed in the substrate. The buried layer comprises an insulating region. A deep trench contact structure is formed in the substrate. The deep trench contact structure comprises a conductive material and a liner layer formed on a side wall of the conductive material. The conductive material is electrically connected with the substrate.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer.

Abstract: The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer.

Abstract: A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer.