Patents by Inventor Jui-Chun Peng
Jui-Chun Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967652Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.Type: GrantFiled: February 16, 2023Date of Patent: April 23, 2024Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: Fu-Chou Liu, Jui-Hung Hsu, Yu-Chiang Peng, Chien-Chen Lee, Ya-Han Chang, Li-Chun Hung
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Publication number: 20230384776Abstract: A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.Type: ApplicationFiled: July 31, 2023Publication date: November 30, 2023Inventors: Yung-Yao LEE, Cheng-Kang HU, Jui-Chun PENG, Hsu-Shui LIU
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Patent number: 11768484Abstract: A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.Type: GrantFiled: March 31, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Yao Lee, Cheng-Kang Hu, Jui-Chun Peng, Hsu-Shui Liu
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Publication number: 20230076566Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: Yung-Yao LEE, Heng-Hsin LIU, Hung-Ming KUO, Jui-Chun PENG
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Patent number: 11500299Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.Type: GrantFiled: August 17, 2020Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Yao Lee, Heng-Hsin Liu, Hung-Ming Kuo, Jui-Chun Peng
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Publication number: 20220317668Abstract: A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Yung-Yao LEE, Cheng-Kang HU, Jui-Chun PENG, Hsu-Shui LIU
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Patent number: 11162777Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.Type: GrantFiled: December 23, 2019Date of Patent: November 2, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hsiang Tseng, Chin-Hsiang Lin, Heng-Hsin Liu, Jui-Chun Peng, Ho-Ping Chen
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Patent number: 11153957Abstract: An electromagnetic radiation generation apparatus includes a collector, a gas supplier and a gas pipeline. The collector has a reflection surface configured to reflect an electromagnetic radiation. The collector includes a bottom portion, a perimeter portion, and a middle portion between the bottom portion and the perimeter portion. The middle portion of the collector includes a plurality of openings. The gas supplier is configured to provide a buffer gas. The gas pipeline is in communication with the gas supplier and the collector, and configured to purge the buffer gas through the openings of the middle portion to form a gas protection layer near the reflection surface of the collector. The openings of the middle portion include a plurality of holes arranged in an array including a plurality of rows of holes, or a plurality of concentric gaps.Type: GrantFiled: July 8, 2019Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tzu Jeng Hsu, Chi-Ming Yang, Chyi Shyuan Chern, Jui-Chun Peng, Heng-Hsin Liu, Chin-Hsiang Lin
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Publication number: 20200379361Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Inventors: Yung-Yao LEE, Heng-Hsin LIU, Hung-Ming KUO, Jui-Chun PENG
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Patent number: 10747128Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.Type: GrantFiled: February 27, 2018Date of Patent: August 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Yao Lee, Heng-Hsin Liu, Hung-Ming Kuo, Jui-Chun Peng
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Publication number: 20200137863Abstract: An electromagnetic radiation generation apparatus includes a collector, a gas supplier and a gas pipeline. The collector has a reflection surface configured to reflect an electromagnetic radiation. The collector includes a bottom portion, a perimeter portion, and a middle portion between the bottom portion and the perimeter portion. The middle portion of the collector includes a plurality of openings. The gas supplier is configured to provide a buffer gas. The gas pipeline is in communication with the gas supplier and the collector, and configured to purge the buffer gas through the openings of the middle portion to form a gas protection layer near the reflection surface of the collector. The openings of the middle portion include a plurality of holes arranged in an array including a plurality of rows of holes, or a plurality of concentric gaps.Type: ApplicationFiled: July 8, 2019Publication date: April 30, 2020Inventors: TZU JENG HSU, CHI-MING YANG, CHYI SHYUAN CHERN, JUI-CHUN PENG, HENG-HSIN LIU, CHIN-HSIANG LIN
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Publication number: 20200132436Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Inventors: Wei-Hsiang Tseng, Chin-Hsiang Lin, Heng-Hsin Liu, Jui-Chun Peng, Ho-Ping Chen
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Patent number: 10514247Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.Type: GrantFiled: January 8, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hsiang Tseng, Chin-Hsiang Lin, Heng-Hsin Liu, Jui-Chun Peng, Ho-Ping Chen
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Publication number: 20190146351Abstract: In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.Type: ApplicationFiled: February 27, 2018Publication date: May 16, 2019Inventors: Yung-Yao LEE, Heng-Hsin LIU, Hung-Ming KUO, Jui-Chun PENG
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Patent number: 10061215Abstract: In a method for fabricating a resist pattern, a substrate coated with a photo resist is loaded on a stage of an exposure apparatus. Underlying patterns are fabricated on the substrate. A surface slope of an exposure area on the substrate is measured. An alignment measurement is performed by detecting an alignment pattern formed in the underlying patterns. An alignment measurement result is corrected based on the measured surface slope. The substrate is aligned to a photo mask by using the corrected alignment measurement result. The photo resist is exposed to radiation passing through the photo mask to form patterns.Type: GrantFiled: June 14, 2016Date of Patent: August 28, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Yao Lee, Jui-Chun Peng, Ho-Ping Chen, Heng-Hsin Liu
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Patent number: 9978625Abstract: A semiconductor method is disclosed. The semiconductor method is performed upon semiconductor wafers, wherein each of the semiconductor wafers includes a first exposure field and a second exposure field, and each of the first exposure field and the second exposure field includes a first alignment mark and a second alignment mark. The method includes: determining a first alignment pattern for a first wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field; performing the aligning operation upon the first semiconductor wafer by using the first alignment pattern; determining a second alignment pattern for a second wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field, wherein the first alignment pattern is different from the second alignment pattern.Type: GrantFiled: June 1, 2016Date of Patent: May 22, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yung-Yao Lee, Jui-Chun Peng, Ho-Ping Chen, Heng-Hsin Liu
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Publication number: 20180128597Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.Type: ApplicationFiled: January 8, 2018Publication date: May 10, 2018Inventors: Wei-Hsiang Tseng, Chin-Hsiang Lin, Heng-Hsin Liu, Jui-Chun Peng, Ho-Ping Chen
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Patent number: 9863754Abstract: A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.Type: GrantFiled: September 15, 2014Date of Patent: January 9, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hsiang Tseng, Chin-Hsiang Lin, Heng-Hsin Liu, Jui-Chun Peng, Ho-Ping Cheng
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Patent number: 9841687Abstract: The present disclosure relates to a method of semiconductor processing. The method includes, receiving a first wafer having a photoresist coating on a face of the first wafer. An exposure unit is used to perform a first number of radiation exposures on the photoresist coating, thereby forming an exposed photoresist coating. The exposed photoresist coating is developed, thereby forming a developed photoresist coating. An OVL measurement zone pattern is selected from a number of different, pre-determined OVL measurement zone patterns based on at least one of: the first number of radiation exposures performed on the first wafer or a previous number of radiation exposures performed on a previously processed wafer, which was processed before the first wafer. A number of OVL measurements are performed on the developed photoresist coating within the selected OVL measurement zone pattern.Type: GrantFiled: July 14, 2015Date of Patent: December 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Yao Lee, Heng-Hsin Liu, Jui-Chun Peng, Yung-Cheng Chen
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Publication number: 20170352564Abstract: A semiconductor method is disclosed. The semiconductor method is performed upon semiconductor wafers, wherein each of the semiconductor wafers includes a first exposure field and a second exposure field, and each of the first exposure field and the second exposure field includes a first alignment mark and a second alignment mark. The method includes: determining a first alignment pattern for a first wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field; performing the aligning operation upon the first semiconductor wafer by using the first alignment pattern; determining a second alignment pattern for a second wafer by selecting one of the alignment marks of the first exposure field, and selecting one of the alignment marks of the second exposure field, wherein the first alignment pattern is different from the second alignment pattern.Type: ApplicationFiled: June 1, 2016Publication date: December 7, 2017Inventors: YUNG-YAO LEE, JUI-CHUN PENG, HO-PING CHEN, HENG-HSIN LIU